公开(公告)号：US20150187436A1

公开(公告)日：2015-07-02

申请号：US14320164

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Bruce QUERBACH ,  William K. LUI ,  David G. ELLIS ,  David J. ZIMMERMAN ,  Theodore Z. SCHOENBORN ,  Christopher W. HAMPSON ,  Ifar WAN ,  Yulan ZHANG

IPC: G11C29/10 ,  G06F11/27 ,  G06F11/263

CPC classification number: G11C29/38 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/18 ,  G11C29/20 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C29/783 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1206 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.

Abstract translation: 根据本说明书，装置包括内部缺陷检测和修复电路，其包括内置于装置内的自检逻辑电路和内置在装置内的自修复逻辑电路。 在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。 在识别一个或多个有缺陷的存储器单元时，内置的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储器单元。 在一个实施例中，作为存储器地址和周期性地址偏移的函数产生数据模式。 本文描述了其它方面。

公开(公告)号：US20220148639A1

公开(公告)日：2022-05-12

申请号：US17441667

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Zhenglong WU ,  Tonia G. MORRIS ,  Christina JUE ,  Daniel BECERRA PEREZ ,  David G. ELLIS

IPC: G11C11/4076 ,  G11C11/4096

Abstract: A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.

公开(公告)号：US20170084351A1

公开(公告)日：2017-03-23

申请号：US15368402

申请日：2016-12-02

Applicant: INTEL CORPORATION

Inventor： Bruce QUERBACH ,  William K. LUI ,  David G. ELLIS ,  David J. ZIMMERMAN ,  Theodore Z. SCHOENBORN ,  Christopher W. HAMPSON ,  Ifar WAN ,  Yulan ZHANG

IPC: G11C29/38 ,  G11C29/44 ,  G11C29/36

CPC classification number: G11C29/38 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/18 ,  G11C29/20 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C29/783 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1206 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.