公开(公告)号：US12153823B2

公开(公告)日：2024-11-26

申请号：US17068369

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Davide Fugazza ,  Dany-Sebastien Ly-Gagnon ,  DerChang Kau

IPC: G11C11/56 ,  G06F3/06 ,  G11C13/00 ,  H10N70/00

Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.

公开(公告)号：US20210050512A1

公开(公告)日：2021-02-18

申请号：US17041882

申请日：2018-05-31

Applicant: Intel Corporation

Inventor： Davide Fugazza ,  Stephen Russell ,  Yao Jin ,  Andrea Redaelli ,  Pengyuan Zheng ,  Yongiun J. Hu

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A phase change memory (PCM) cell (100) includes a PCM layer (105), a metal ceramic composite material layer (120), and a carbon nitride (CNX) electrode layer (110) disposed between the PCM material layer and the metal ceramic composite material layer. The CNX electrode layer can have an electrical resistivity at room temperature of from about 1 mOhm-cm to about 2000 mOhm-cm and an electrical resistivity at 650° C. of from about 1 mOhm-cm to about 100 mOhm-cm.

公开(公告)号：US09613698B2

公开(公告)日：2017-04-04

申请号：US15154465

申请日：2016-05-13

Applicant: INTEL CORPORATION

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Gerard H. Joyce ,  Prashant Damle ,  Derchang Kau ,  Davide Fugazza

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0092

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US20220180934A1

公开(公告)日：2022-06-09

申请号：US17114980

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Davide Fugazza ,  Dany-Sebastien Ly-Gagnon

IPC: G11C16/20 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells assigned to a plurality of groups, wherein each group is associated with a respective at least one program pulse parameter based on programming responses of memory cells of that group; and access circuitry to program a memory cell of a first group of the plurality of groups to a first program state by applying a program pulse having the at least one program pulse parameter associated with the first group.

公开(公告)号：US20220113892A1

公开(公告)日：2022-04-14

申请号：US17068369

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Davide Fugazza ,  Dany-Sebastien Ly-Gagnon ,  DerChang Kau

IPC: G06F3/06 ,  G11C11/56 ,  G11C13/00

Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.

公开(公告)号：US11264567B2

公开(公告)日：2022-03-01

申请号：US16688309

申请日：2019-11-19

Applicant: INTEL CORPORATION

Inventor： Srivatsan Venkatesan ,  Davide Mantegazza ,  John Gorman ,  Iniyan Soundappa Elango ,  Davide Fugazza ,  Andrea Redaelli ,  Fabio Pellizzer

IPC: H01L45/00 ,  H01L27/24

Abstract: Various embodiments of a three-dimensional cross-point (3D X-point) memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

公开(公告)号：US20160254052A1

公开(公告)日：2016-09-01

申请号：US15154465

申请日：2016-05-13

Applicant: INTEL CORPORATION

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Gerard H. Joyce ,  Prashant Damle ,  Derchang Kau ,  Davide Fugazza

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0092

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US09368205B2

公开(公告)日：2016-06-14

申请号：US14010417

申请日：2013-08-26

Applicant: INTEL CORPORATION

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Gerard H. Joyce ,  Prashant Damle ,  Derchang Kau ,  Davide Fugazza

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0092

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了在相变存储器（PCM）设备中的字线路径隔离的技术和配置。 在一个实施例中，一种方法包括增加通过相变存储器（PCM）器件的存储器单元的电流，其中存储器单元与电容器耦合，并且随后增加电流，产生通过存储器单元的瞬态电流，由 放电电容器来重置存储单元。 在另一个实施例中，一种方法包括增加通过相变存储器（PCM）器件的存储器单元的电流，并且控制电流大于阈值电流并且低于存储器单元的保持电流以设置存储器单元。 可以描述和/或要求保护其他实施例。