公开(公告)号：US20190123164A1

公开(公告)日：2019-04-25

申请号：US16230454

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US10431661B2

公开(公告)日：2019-10-01

申请号：US15778304

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US11824002B2

公开(公告)日：2023-11-21

申请号：US16457712

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Walid M. Hafez ,  Chia-Hong Jan ,  Jiansheng Xu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209

Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.

公开(公告)号：US10923574B2

公开(公告)日：2021-02-16

申请号：US16569879

申请日：2019-09-13

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US10204999B2

公开(公告)日：2019-02-12

申请号：US15743847

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L21/764 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US11114538B2

公开(公告)日：2021-09-07

申请号：US16230454

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L21/764 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US10535747B2

公开(公告)日：2020-01-14

申请号：US15778306

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/764 ,  H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as -shape or -shape, for example.

公开(公告)号：US20180197966A1

公开(公告)日：2018-07-12

申请号：US15743847

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/764 ,  H01L21/768

CPC classification number: H01L29/4991 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/78

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.