公开(公告)号：US10431661B2

公开(公告)日：2019-10-01

申请号：US15778304

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US11264329B2

公开(公告)日：2022-03-01

申请号：US16074142

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L23/538 ,  H01L21/768

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

公开(公告)号：US10903372B2

公开(公告)日：2021-01-26

申请号：US15770009

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L29/8605 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: Metal-oxide-polysilicon tunable resistors and methods of fabricating metal-oxide-polysilicon tunable resistors are described. In an example, a tunable resistor includes a polysilicon resistor structure disposed above a substrate. A gate oxide layer is disposed on the polysilicon resistor structure. A metal gate layer is disposed on the gate oxide layer.

公开(公告)号：US11737362B2

公开(公告)日：2023-08-22

申请号：US16074151

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L35/14 ,  H10N10/10 ,  H10N10/17 ,  H10N10/81 ,  H10N10/851 ,  H10N19/00 ,  H01L29/78

CPC classification number: H10N10/10 ,  H01L29/785 ,  H10N10/17 ,  H10N10/81 ,  H10N10/851 ,  H10N19/00

Abstract: An apparatus includes a first semiconductor fin and a second semiconductor fin that is parallel to the first semiconductor fin. The first semiconductor fin extends from a first region of a substrate near a circuit that produces thermal energy when a circuit is in operation to a second region of the substrate, which is disposed away from the circuit. The second semiconductor fin extends from the first region to the second region and has a different material composition than the first semiconductor fin. The first and second semiconductor fins collectively exhibit a Seebeck effect when the circuit is in operation. The apparatus includes interconnects to couple the first and second semiconductor fins to a power supply circuit to transfer electricity generated due to the Seebeck effect to the power supply circuit.

公开(公告)号：US20220157729A1

公开(公告)日：2022-05-19

申请号：US17649637

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L23/538 ,  H01L21/768

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

公开(公告)号：US10923574B2

公开(公告)日：2021-02-16

申请号：US16569879

申请日：2019-09-13

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US11830818B2

公开(公告)日：2023-11-28

申请号：US17649637

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5386

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

公开(公告)号：US11063137B2

公开(公告)日：2021-07-13

申请号：US16302698

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Jui-Yen Lin ,  Chen-Guan Lee ,  Joodong Park ,  Walid M. Hafez ,  Kun-Huan Shih

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/265

Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

公开(公告)号：US20210074642A1

公开(公告)日：2021-03-11

申请号：US16074142

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L23/538 ,  H01L21/768

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

公开(公告)号：US20190123170A1

公开(公告)日：2019-04-25

申请号：US16302698

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Jui-Yen Lin ,  Chen-Guan Lee ,  Joodong Park ,  Walid M. Hafez ,  Kun-Huan Shih

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L27/088

Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.