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1.
公开(公告)号:US11695008B2
公开(公告)日:2023-07-04
申请号:US16846896
申请日:2020-04-13
Applicant: Intel Corporation
Inventor: Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
IPC: H01L27/092 , H01L29/66 , H01L29/78 , H01L29/40 , H01L21/8234 , H01L27/088 , H01L29/49 , H01L21/28 , H01L29/423 , H01L29/51
CPC classification number: H01L27/0922 , H01L21/823431 , H01L21/823456 , H01L21/823462 , H01L27/0886 , H01L27/0924 , H01L29/408 , H01L29/40114 , H01L29/42364 , H01L29/4966 , H01L29/66484 , H01L29/66795 , H01L29/7855 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7831 , H01L29/7851
Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
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2.
公开(公告)号:US11121040B2
公开(公告)日:2021-09-14
申请号:US16317265
申请日:2016-09-30
Applicant: Intel Corporation
Inventor: Chen-Guan Lee , Everett S. Cassidy-Comfort , Joodong Park , Walid M. Hafez , Chia-Hong Jan , Rahul Ramaswamy , Neville L. Dias , Hsu-Yu Chang
IPC: H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L21/28 , H01L21/3213 , H01L21/265 , H01L21/3115 , H01L29/66 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L27/088 , H01L29/10 , H01L27/02
Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.
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公开(公告)号:US10784378B2
公开(公告)日:2020-09-22
申请号:US16318108
申请日:2016-09-30
Applicant: Intel Corporation
Inventor: Walid M. Hafez , Roman W. Olac-Vaw , Joodong Park , Chen-Guan Lee , Chia-Hong Jan , Everett S. Cassidy-Comfort
IPC: H01L27/088 , H01L29/78 , H01L21/84 , H01L27/12 , H01L29/417 , H01L29/66
Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.
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公开(公告)号:US20190123164A1
公开(公告)日:2019-04-25
申请号:US16230454
申请日:2018-12-21
Applicant: Intel Corporation
Inventor: Chen-Guan Lee , Joodong Park , En-Shao Liu , Everett S. Cassidy-Comfort , Walid M. Hafez , Chia-Hong Jan
IPC: H01L29/49 , H01L21/768 , H01L29/66 , H01L29/78 , H01L21/764
Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.
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公开(公告)号:US09806095B2
公开(公告)日:2017-10-31
申请号:US14975645
申请日:2015-12-18
Applicant: Intel Corporation
Inventor: Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC: H01L21/84 , H01L27/12 , H01L29/66 , H01L21/8234 , H01L21/02 , H01L21/28 , H01L29/423 , H01L29/51
CPC classification number: H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
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公开(公告)号:US12136628B2
公开(公告)日:2024-11-05
申请号:US18538795
申请日:2023-12-13
Applicant: Intel Corporation
Inventor: Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC: H01L27/12 , H01L21/02 , H01L21/28 , H01L21/8234 , H01L21/84 , H01L29/423 , H01L29/51 , H01L29/66
Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
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公开(公告)号:US11114538B2
公开(公告)日:2021-09-07
申请号:US16230454
申请日:2018-12-21
Applicant: Intel Corporation
Inventor: Chen-Guan Lee , Joodong Park , En-Shao Liu , Everett S. Cassidy-Comfort , Walid M. Hafez , Chia-Hong Jan
IPC: H01L29/49 , H01L21/764 , H01L29/66 , H01L29/78 , H01L21/768
Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.
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公开(公告)号:US10535747B2
公开(公告)日:2020-01-14
申请号:US15778306
申请日:2015-12-23
Applicant: INTEL CORPORATION
Inventor: En-Shao Liu , Joodong Park , Chen-Guan Lee , Chia-Hong Jan
IPC: H01L29/49 , H01L21/28 , H01L21/764 , H01L29/78 , H01L29/66
Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as -shape or -shape, for example.
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公开(公告)号:US10304681B2
公开(公告)日:2019-05-28
申请号:US15573458
申请日:2015-06-22
Applicant: Intel Corporation
Inventor: Chen-Guan Lee , Lu Yang , Joodong Park , Chia-Hong Jan
IPC: H01L29/78 , H01L21/225 , H01L29/66 , H01L27/088 , H01L29/06
Abstract: Dual height glass is described for doping a fin of a field effect transistor structure in an integrated circuit. In one example, a method includes applying a glass layer over a fin of a FinFET structure, the fin having a source/drain region and a gate region, applying a polysilicon layer over the gate region, removing a portion of the glass layer from the source/drain region after applying the polysilicon, and thermally annealing the glass to drive dopants into the fin, and applying an epitaxial layer over the source/drain region.
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公开(公告)号:US20190006279A1
公开(公告)日:2019-01-03
申请号:US15748608
申请日:2015-08-26
Applicant: Intel Corporation
Inventor: Chen-Guan Lee , Vadym Kapinus , Pei-Chi Liu , Joodong Park , Walid M. Hafez , Chia-Hong Jan
IPC: H01L23/522 , H01L27/06 , H01L49/02 , H01L29/78 , H01L21/86 , H01L29/786
CPC classification number: H01L23/5228 , H01L21/86 , H01L27/0629 , H01L28/00 , H01L28/22 , H01L28/24 , H01L29/785 , H01L29/78657
Abstract: IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.
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