公开(公告)号：US20250120143A1

公开(公告)日：2025-04-10

申请号：US18482192

申请日：2023-10-06

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Adam Brand ,  Chen-Guan Lee ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Adithya Shankar ,  Marko Radosavljevic

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: Described herein are gate-all-around (GAA) transistors with extended drains, where the drain region extends through a well region below the GAA transistor. A high voltage can be applied to the drain, and the extended drain region provides a voltage drop. The transistor length (and, specifically length of the extended drain) can be varied based on the input voltage to the device, e.g., providing a longer drain for higher input voltages. The extended drain transistors can be implemented in devices that include CFETs, either by implementing the extended drain transistor across both CFET layers, or by providing a sub-fin pedestal with the well regions in the lower layer.

公开(公告)号：US11430778B2

公开(公告)日：2022-08-30

申请号：US16354741

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Chen-Guan Lee

IPC: H01L27/02 ,  H01L21/768

Abstract: An integrated circuit structure comprises a plurality of structures above a substrate, wherein spacing between the structures creates a range of different open density regions from a relatively low open density region to a high open density region. A first fill material fills at least a portion of openings between the structures in at least the high open density region to provide a substantially uniform open density across the different open density regions, wherein the first fill material is patterned to include openings therein. A second fill material fills the openings between the structures in the low open density region, and fills the openings in the first fill material in the at least the high open density region.

公开(公告)号：US10559688B2

公开(公告)日：2020-02-11

申请号：US16081215

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Chen-Guan Lee ,  Walid M. Hafez ,  Joodong Park ,  Chia-Hong Jan ,  Hsu-Yu Chang

IPC: H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.

公开(公告)号：US10431661B2

公开(公告)日：2019-10-01

申请号：US15778304

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US09748327B2

公开(公告)日：2017-08-29

申请号：US15129794

申请日：2014-06-18

Applicant: INTEL CORPORATION

Inventor： Chen-Guan Lee ,  Walid Hafez ,  Chia-Hong Jan

IPC: G11C11/00 ,  H01L45/00 ,  H01L49/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L23/66

CPC classification number: H01L28/20 ,  H01L21/8234 ,  H01L23/66 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/24 ,  H01L29/785

Abstract: Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

公开(公告)号：US11967615B2

公开(公告)日：2024-04-23

申请号：US15773536

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Hsu-Yu Chang ,  Neville L. Dias ,  Walid M. Hafez ,  Chia-Hong Jan ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/161 ,  H01L29/165

Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

公开(公告)号：US11121040B2

公开(公告)日：2021-09-14

申请号：US16317265

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Everett S. Cassidy-Comfort ,  Joodong Park ,  Walid M. Hafez ,  Chia-Hong Jan ,  Rahul Ramaswamy ,  Neville L. Dias ,  Hsu-Yu Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02

Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.

公开(公告)号：US11075286B2

公开(公告)日：2021-07-27

申请号：US16344003

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Neville L. Dias ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/08 ,  H01L29/10

Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.

公开(公告)号：US10964690B2

公开(公告)日：2021-03-30

申请号：US16474896

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Hsu-Yu Chang ,  Neville L. Dias ,  Rahul Ramaswamy ,  Nidhi Nidhi ,  Chen-Guan Lee

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L49/02

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.

公开(公告)号：US10784378B2

公开(公告)日：2020-09-22

申请号：US16318108

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Roman W. Olac-Vaw ,  Joodong Park ,  Chen-Guan Lee ,  Chia-Hong Jan ,  Everett S. Cassidy-Comfort

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66

Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.