公开(公告)号：US20190303300A1

公开(公告)日：2019-10-03

申请号：US16442267

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： James A. BOYD ,  Robert J. ROYER, JR. ,  Lily P. LOOI ,  Gary C. CHOW ,  Zvika GREENFIELD ,  Chia-Hung S. KUO ,  Dale J. JUENEMANN

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.

公开(公告)号：US20190251023A1

公开(公告)日：2019-08-15

申请号：US16248158

申请日：2019-01-15

Applicant: Intel Corporation

Inventor： James A. BOYD ,  Dale J. JUENEMANN ,  Francis R. CORRADO

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12

CPC classification number: G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F2212/205 ,  G06F2212/217 ,  G06F2212/222 ,  G06F2212/60

Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.

公开(公告)号：US20190042415A1

公开(公告)日：2019-02-07

申请号：US16006484

申请日：2018-06-12

Applicant: Intel Corporation

Inventor： James A. BOYD ,  Dale J. JUENEMANN

IPC: G06F12/0804 ,  G06F12/1045 ,  G06F9/30

Abstract: A processor is described. The processor includes register space to accept input parameters of a software command to move a data item out of computer system storage and into persistent system memory. The input parameters include an identifier of a software process that desires access to the data item in the persistent system memory and a virtual address of the data item referred to by the software process.

公开(公告)号：US20190042414A1

公开(公告)日：2019-02-07

申请号：US15976795

申请日：2018-05-10

Applicant: Intel Corporation

Inventor： Dale J. JUENEMANN ,  James A. BOYD ,  Robert J. ROYER, JR.

IPC: G06F12/0804 ,  G06F3/06

Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.

公开(公告)号：US20220114086A1

公开(公告)日：2022-04-14

申请号：US17560007

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Chace A. CLARK ,  James A. BOYD ,  Chet R. DOUGLAS ,  Andrew M. RUDOFF ,  Dan J. WILLIAMS

IPC: G06F12/02

Abstract: Examples include techniques to expand system memory via use of available device memory. Circuitry at a device coupled to a host device partitions a portion of memory capacity of a memory configured for use by compute circuitry resident at the device to execute a workload. The partitioned portion of memory capacity is reported to the host device as being available for use as a portion of system memory. An indication from the host device is received if the portion of memory capacity has been identified for use as a first portion of pooled system memory. The circuitry to monitor usage of the memory capacity used by the compute circuitry to execute the workload to decide whether to place a request to the host device to reclaim the memory capacity from the first portion of pooled system memory.

公开(公告)号：US20210232504A1

公开(公告)日：2021-07-29

申请号：US17227220

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： James A. BOYD ,  Christopher E. COX ,  Nikhil TALPALLIKAR

IPC: G06F12/0891 ,  G06F12/0882 ,  G06F12/1081 ,  G06F12/1009 ,  G06F1/3234 ,  G06F11/30 ,  G06F11/32

Abstract: A memory subsystem with memory managed with coherent access can manage page table entries to enable putting the memory in a low power state. The memory control can change a page table entry for the memory prior to triggering the memory to enter the low power state. The change to the page table entry will cause a page fault for a subsequent access to the memory. The page fault will trigger handling the access to the memory with a fault routine, avoiding synchronous delay to the memory that would occur with normal access.

公开(公告)号：US20170351452A1

公开(公告)日：2017-12-07

申请号：US15170879

申请日：2016-06-01

Applicant: INTEL CORPORATION

Inventor： James A. BOYD ,  John W. CARROLL ,  Sanjeev N. TRIKA

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/311 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7208

Abstract: In one embodiment, dynamic host memory buffer allocation in accordance with the present description includes sensing a level of activity of a memory or storage and dynamically allocating a portion of a host memory as a buffer to the non-volatile memory, as a function of a sensed level of activity of the non-volatile memory. Such dynamic allocation of host memory buffers as a function of sensed levels of activity, can improve the efficiency of the allocation of memory resources and improve system performance. Other aspects are described herein.