公开(公告)号：US09223668B2

公开(公告)日：2015-12-29

申请号：US13800185

申请日：2013-03-13

Applicant: INTEL CORPORATION

Inventor： Ki Yoon ,  Robert De Gruijl ,  Chai Ziv ,  Michael Klinglesmith

IPC: G06F11/00 ,  G06F11/26 ,  G06F11/273 ,  G06F11/36

CPC classification number: G06F11/26 ,  G06F11/2733 ,  G06F11/3636 ,  G06F11/3648

Abstract: A fabric trace hook is disclosed to enable debugging operations of agents operating in a peer-to-peer integrated on-chip system fabric. The fabric trace hook, embedded within the IOSF, includes programmable triggering and capturing logic, timestamp capability, and a security feature to disallow tracing of proprietary transactions. The fabric trace hook may operate in a lossy or lossless mode.

Abstract translation: 公开了一种织物跟踪钩，以便能够在对等集成片上系统结构中操作的代理的调试操作。 嵌入在IOSF中的结构跟踪钩子包括可编程触发和捕获逻辑，时间戳功能和安全功能，以禁止跟踪专有交易。 织物跟踪钩可以在有损或无损模式下操作。

公开(公告)号：US09690353B2

公开(公告)日：2017-06-27

申请号：US13799524

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Douglas Moran ,  Achmed Rumi Zahir ,  William Knolla ,  Hartej Singh ,  Vasudev Vasu Bibikar ,  Sanjeev Jahagirdar ,  Michael Klinglesmith ,  Irwin Vaz ,  Varghese George

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.

公开(公告)号：US09122811B2

公开(公告)日：2015-09-01

申请号：US13968504

申请日：2013-08-16

Applicant: INTEL CORPORATION

Inventor： Michael Klinglesmith ,  Mohan Nair ,  Joseph Murray

IPC: H04L12/66 ,  G06F13/00 ,  G06F13/40 ,  H04L12/64 ,  H04L12/18 ,  H04L12/40 ,  G06F13/42 ,  G06F13/10 ,  H04L29/08

CPC classification number: G06F13/4027 ,  G06F13/105 ,  G06F13/4221 ,  G06F2213/0026 ,  H04L12/1845 ,  H04L12/40032 ,  H04L12/6418 ,  H04L29/08468 ,  H04L67/1078

Abstract: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明涉及一种具有耦合在上游结构和集成设备结构之间的虚拟端口的集成端点，该虚拟端口包括多功能逻辑，以处理与一个或多个知识产权（IP） 集成设备结构。 集成设备结构具有在IP块和上行结构之间传送数据和命令信息的主要信道和用于在IP块和多功能逻辑之间传送边带信息的边带信道。 描述和要求保护其他实施例。