公开(公告)号：US09042652B2

公开(公告)日：2015-05-26

申请号：US13666913

申请日：2012-11-01

Applicant: Intel Corporation

Inventor： Niraj Gupta ,  Oren Agam ,  Benny Eitan ,  Mostafa Hagog

IPC: G06K9/34 ,  G06K9/46 ,  G06T7/00

CPC classification number: G06K9/4638 ,  G06T7/11 ,  G06T7/187 ,  G06T2200/28

Abstract: An apparatus may include a memory, a processor circuit, and a connected component labeling module. The connected component labeling module may be operative of the processor circuit to determine one or more connected components during reading of an image comprising a multiplicity of pixels from the memory, assign a label to a plurality of pixels of the multiplicity of pixels, generate one or more label connections for a respective one or more labels, each label connection linking a higher label to a lowest label for the same connected component, and write to the memory for each label of the one or more labels a lowest label as defined by the label connection for the each label after a label is assigned to each pixel.

Abstract translation: 装置可以包括存储器，处理器电路和连接的部件标签模块。 连接的组件标注模块可操作于处理器电路，以在从存储器读取包括多个像素的图像的读取期间确定一个或多个连接的组件，将标签分配给多个像素的多个像素，生成一个或多个 针对相应的一个或多个标签的更多标签连接，每个标签连接将较高标签链接到相同连接部件的最低标签，并且向该存储器写入一个或多个标签的每个标签，该标签由标签定义 将标签分配给每个像素后，每个标签的连接。

公开(公告)号：US10726583B2

公开(公告)日：2020-07-28

申请号：US15395495

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Ajit Singh ,  Bharat Daga ,  Oren Agam ,  Michael Behar ,  Dmitri Vainbrand

IPC: G06T9/00 ,  G06N3/08 ,  G06N3/04 ,  G06F13/10 ,  G06T15/00 ,  G06T1/20

Abstract: Embodiments described herein provide a processing apparatus comprising compute logic to generate output feature map data for a convolutional neural network (CNN) and write the feature map data to a memory buffer; a direct memory access (DMA) controller including a feature map encoder, the DMA controller to read the feature map data from the memory buffer, encode the feature map data using one of multiple encode algorithms, and write encoded feature map data to memory coupled with the processing apparatus; and wherein the compute logic is to read the encoded feature map data from the memory in an encoded format and decode the encoded feature map data while reading the encoded feature map data.

公开(公告)号：US20230333913A1

公开(公告)日：2023-10-19

申请号：US18309650

申请日：2023-04-28

Applicant: INTEL CORPORATION

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/50 ,  G06F16/901 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06F9/5083 ,  G06F16/9024 ,  G06N3/044 ,  G06N3/045

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

公开(公告)号：US11847497B2

公开(公告)日：2023-12-19

申请号：US17561500

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/46 ,  G06F9/50 ,  G06F3/06

CPC classification number: G06F9/5016 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/505

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

公开(公告)号：US20220197703A1

公开(公告)日：2022-06-23

申请号：US17561500

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/50 ,  G06F3/06

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

公开(公告)号：US11231963B2

公开(公告)日：2022-01-25

申请号：US16542012

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/46 ,  G06F9/50 ,  G06F3/06

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

公开(公告)号：US12217101B2

公开(公告)日：2025-02-04

申请号：US18309650

申请日：2023-04-28

Applicant: INTEL CORPORATION

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/50 ,  G06F16/901 ,  G06N3/044 ,  G06N3/045

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

公开(公告)号：US11675630B2

公开(公告)日：2023-06-13

申请号：US16541979

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Michael Behar ,  Moshe Maor ,  Ronen Gabbai ,  Roni Rosner ,  Zigi Walter ,  Oren Agam

IPC: G06F9/50 ,  G06F16/901 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06F9/5083 ,  G06F16/9024 ,  G06N3/044 ,  G06N3/045

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.