公开(公告)号：US20180323106A1

公开(公告)日：2018-11-08

申请号：US15774446

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC ,  SANAZ GARDNER ,  SEUNG HOON SUNG

IPC: H01L21/8258 ,  H01L27/06 ,  H01L27/085

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7786

Abstract: Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some embodiments, a Si substrate may be patterned with recessed trenches located under corresponding openings formed in a dielectric layer over the substrate. Within each recessed trench, a stack including a buffer layer, a GaN or indium gallium nitride (InGaN) layer, and a polarization layer may be selectively formed, in accordance with some embodiments. The p-channel stack further may include another GaN or InGaN layer over its polarization layer, with source/drain (S/D) portions adjacent the m-plane or a-plane sidewalls of that GaN or InGaN layer. The n-channel may include S/D portions over its GaN or InGaN layer, within its polarization layer, in accordance with some embodiments. Gate stack placement can be customized to provide any desired combination of enhancement and depletion modes for the resultant neighboring p-channel and n-channel transistor devices.

公开(公告)号：US20190214464A1

公开(公告)日：2019-07-11

申请号：US15772742

申请日：2015-12-14

Applicant: INTEL CORPORATION

Inventor： MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  SANAZ GARDNER ,  SEUNG HOON SUNG

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/10 ,  H01L21/30612 ,  H01L21/3086 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7786

Abstract: Techniques are disclosed for producing integrated circuit structures that include one or more geometrically manipulated polarization layers. The disclosed structures can be formed, for instance, using spacer erosion methods in which more than one type of spacer material is deposited on a polarization layer, and the spacer materials and underlying regions of the polarization layer may then be selectively etched in sequence to provide a desired profile shape to the polarization layer. Geometrically manipulated polarization layers as disclosed herein may be formed to be thinner in regions closer to the gate than in other regions, in some embodiments. The disclosed structures may eliminate the need for a field plate and may also be configured with polarization layers that are shorter in lateral length than polarization layers of uniform thickness without sacrificing performance capability. Additionally, the disclosed techniques may provide increased voltage breakdown without sacrificing Ron.

公开(公告)号：US20180331082A1

公开(公告)日：2018-11-15

申请号：US15777500

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  SANAZ GARDNER

IPC: H01L25/16 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/08 ,  H01L29/778 ,  H01L29/20 ,  H01L29/423

Abstract: Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor materials, such as gallium nitride, indium nitride, aluminum nitride, and mixtures thereof. The disclosed semiconductor structures may further include a CMOS portion implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). The disclosed techniques can be used to form highly-efficient envelope tracking devices that include a voltage regulator and a radio frequency (RF) power amplifier that may both be located on the III-N portion of the semiconductor structure. Either of the CMOS or III-N portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of a III-N voltage regulator and RF power amplifier along with column IV CMOS devices on a single substrate.