公开(公告)号：US09916876B2

公开(公告)日：2018-03-13

申请号：US14336128

申请日：2014-07-21

Applicant: INTEL CORPORATION

Inventor： Suketu R. Partiwala ,  Prashanth Kalluraya ,  Bruce L. Fleming ,  Shreekant S. Thakkar ,  Kenneth D. Shoemaker ,  Sridhar Lakshmanamurthy ,  Sami Yehia ,  Joydeep Ray

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/18 ,  G06F1/32

CPC classification number: G11C5/148 ,  G06F1/189 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3275 ,  Y02D10/14

Abstract: An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

公开(公告)号：US10768680B2

公开(公告)日：2020-09-08

申请号：US15678025

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nivedha Krishnakumar ,  Youvedeep Singh ,  Suketu R. Partiwala

IPC: G06F1/00 ,  G06F1/3206 ,  G06F9/30 ,  G06F1/3287 ,  G06F9/52 ,  G06F1/3203

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

公开(公告)号：US09733689B2

公开(公告)日：2017-08-15

申请号：US14752896

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nivedha Krishnakumar ,  Youvedeep Singh ,  Suketu R. Partiwala

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/30 ,  G06F9/52

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/52 ,  Y02D10/171

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

公开(公告)号：US20180059766A1

公开(公告)日：2018-03-01

申请号：US15678025

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Rajeev D. Muralidhar ,  Harinarayanan Seshadri ,  Nivedha Krishnakumar ,  Youvedeep Singh ,  Suketu R. Partiwala

IPC: G06F1/32 ,  G06F9/52 ,  G06F9/30

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.