公开(公告)号：US09916876B2

公开(公告)日：2018-03-13

申请号：US14336128

申请日：2014-07-21

Applicant: INTEL CORPORATION

Inventor： Suketu R. Partiwala ,  Prashanth Kalluraya ,  Bruce L. Fleming ,  Shreekant S. Thakkar ,  Kenneth D. Shoemaker ,  Sridhar Lakshmanamurthy ,  Sami Yehia ,  Joydeep Ray

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/18 ,  G06F1/32

CPC classification number: G11C5/148 ,  G06F1/189 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3275 ,  Y02D10/14

Abstract: An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

公开(公告)号：US20150134873A1

公开(公告)日：2015-05-14

申请号：US14594293

申请日：2015-01-12

Applicant: Intel Corporation

Inventor： Bruce L. Fleming ,  Achmed R. Zahir ,  Arvind Mandhani ,  Satish B. Acharya

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/20 ,  G06F13/385 ,  G06F13/404 ,  G06F13/42 ,  G06F13/4221

Abstract: An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modern PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Abstract translation: 一个实施例将非PCI兼容设备与PCI兼容的操作系统集成。 织物系统模拟PCI的行为。 当非PCI兼容设备不知道如何响应PCI枚举时，实施例提供PCI枚举应答，并因此模拟在仿真期间通常来自PCI兼容设备的应答。 实施例允许系统设计者将非标准结构结构结合在一起，从而在现代PCI兼容操作系统中仍然使用强大且成熟的PCI基础架构。 更一般地，实施例允许符合第一标准（但不是第二标准）的操作系统发现并与不符合第一标准（但可能符合第二标准）的设备进行通信。 本文描述了其它实施例。

公开(公告)号：US20160139936A1

公开(公告)日：2016-05-19

申请号：US14998156

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Uttam K. Sengupta ,  Shreekant S. Thakkar ,  Bruce L. Fleming ,  Uma M. Gadamsetty ,  Arvind Mandhani ,  Shane D. Wall

IPC: G06F9/44 ,  H04B1/3877 ,  G06F13/40 ,  H04B1/3883

CPC classification number: G06F9/4408 ,  G06F9/441 ,  G06F13/4081 ,  H04B1/3877 ,  H04B1/3883 ,  Y02D10/14 ,  Y02D10/151

Abstract: Embodiments of a method and apparatus are described for operating a mobile computing device in different modes using different operating systems. An apparatus may comprise, for example, a memory operative to store multiple operating systems, a processor operative to execute the multiple operating systems, an operating system management module operative to select a first operating system when the mobile computing device is in a first mode or a second operating system when the mobile computing device is in a second mode and the mobile computing device is coupled to one or more external devices. Other embodiments are described and claimed.

Abstract translation: 描述了用于使用不同操作系统以不同模式操作移动计算设备的方法和装置的实施例。 设备可以包括例如可操作地存储多个操作系统的存储器，可操作以执行多个操作系统的处理器，当移动计算设备处于第一模式时操作以选择第一操作系统的操作系统管理模块，或者 当移动计算设备处于第二模式并且移动计算设备耦合到一个或多个外部设备时，第二操作系统。 描述和要求保护其他实施例。

公开(公告)号：US09665522B2

公开(公告)日：2017-05-30

申请号：US14594293

申请日：2015-01-12

Applicant: Intel Corporation

Inventor： Bruce L. Fleming ,  Achmed R. Zahir ,  Arvind Mandhani ,  Satish B. Acharya

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/20 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4027 ,  G06F13/20 ,  G06F13/385 ,  G06F13/404 ,  G06F13/42 ,  G06F13/4221

Abstract: An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modern PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

公开(公告)号：US09665155B2

公开(公告)日：2017-05-30

申请号：US14366177

申请日：2013-12-28

Applicant: Intel Corporation

Inventor： Uttam K. Sengupta ,  Rajasekaran Andiappan ,  Prashanth Kalluraya ,  Bruce L. Fleming

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/32 ,  G06F1/3243 ,  G06F9/5094 ,  Y02D10/22

Abstract: Methods and apparatus relating to increasing energy efficiency of sensor controllers are described. In an embodiment, logic (e.g., within a sensor controller) performs one or more tasks corresponding to acquisition of data from one or more sensors. The logic performs the one or more tasks to allow a processor core of the sensor controller to enter (or stay in) a low power consumption state during performance of the one or more data acquisition tasks. Other embodiments are also disclosed and claimed.

公开(公告)号：US20140258749A1

公开(公告)日：2014-09-11

申请号：US14128945

申请日：2012-11-27

Applicant: INTEL CORPORATION

Inventor： Ren Wamg ,  Tsung-Yuan C. Tai ,  Jr-Shian Tsai ,  Bruce L. Fleming ,  Rajeev D. Muralidhar ,  Mesut A. Ergin ,  Prakash N. Iyer ,  Harinarayanan Seshadri

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

Abstract: Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination.

Abstract translation: 系统和方法可以提供用于识别与平台的活动工作负载相关联的运行时间信息，以及至少部分地基于运行时信息来为该平台进行主动空闲状态确定。 此外，平台上的共享资源的低功率状态可以至少部分地基于主动空闲状态确定与主动工作负载的执行同时被控制。

公开(公告)号：US10282344B2

公开(公告)日：2019-05-07

申请号：US15122575

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Sundar Iyer ,  Rajasekaran Andiappan ,  Ajaya V. Durg ,  Kenneth P. Foust ,  Bruce L. Fleming

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/3287 ,  G06F13/26 ,  G06F13/364

Abstract: In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.

公开(公告)号：US20170103036A1

公开(公告)日：2017-04-13

申请号：US15122575

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Sundar Iyer ,  Rajasekaran Andiappan ,  Ajaya V. Durg ,  Kenneth P. Foust ,  Bruce L. Fleming

IPC: G06F13/42 ,  G06F13/40 ,  G06F1/32 ,  G06F13/364 ,  G06F13/26

CPC classification number: G06F13/4282 ,  G06F1/3287 ,  G06F13/26 ,  G06F13/364 ,  G06F13/404 ,  G06F13/4295 ,  G06F2213/0016

Abstract: In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.

公开(公告)号：US08959531B2

公开(公告)日：2015-02-17

申请号：US14105770

申请日：2013-12-13

Applicant: Intel Corporation

Inventor： Ren Wang ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Mesut A. Ergin ,  Prakash N. Iyer ,  Bruce L. Fleming

IPC: G06F13/00 ,  G06F9/54 ,  G06F1/32

CPC classification number: G06F9/4881 ,  G06F1/3203 ,  G06F9/54 ,  G06F9/542

Abstract: Systems and methods of managing break events may provide for detecting a first break event from a first event source and detecting a second break event from a second event source. In one example, the event sources can include devices coupled to a platform as well as active applications on the platform. Issuance of the first and second break events to the platform can be coordinated based on at least in part runtime information associated with the platform.

Abstract translation: 管理中断事件的系统和方法可以提供从第一事件源检测第一中断事件并从第二事件源检测第二中断事件。 在一个示例中，事件源可以包括耦合到平台的设备以及平台上的活动应用。 可以基于至少部分与平台相关联的运行时信息来协调向平台发出第一和第二休息事件。

公开(公告)号：US08719612B2

公开(公告)日：2014-05-06

申请号：US13736829

申请日：2013-01-08

Applicant: Intel Corporation

Inventor： Bruce L. Fleming ,  Ashish V. Choubal ,  Sanjoy K. Mondal ,  Belliappa M. Kuttanna

IPC: G06F1/00

CPC classification number: G06F1/3287 ,  G06F1/3203

Abstract: A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.

Abstract translation: 一种用于保存和/或检索用于电力状态转换的处理器核心的上下文信息的方法和系统。 处理器核心驻留在多个功率状态之间不同地转换的复杂功率域。 处理器核心包括用于存储和检索处理器核心上下文信息的本地上下文存储区域。 低功耗上下文存储位于复合功率域外的标称功率域。 基于复电力域的功率状态转换是否包括向处理器核心断电的过渡，将处理器核心的上下文信息存储到低功率上下文存储器。