公开(公告)号：US09916876B2

公开(公告)日：2018-03-13

申请号：US14336128

申请日：2014-07-21

Applicant: INTEL CORPORATION

Inventor： Suketu R. Partiwala ,  Prashanth Kalluraya ,  Bruce L. Fleming ,  Shreekant S. Thakkar ,  Kenneth D. Shoemaker ,  Sridhar Lakshmanamurthy ,  Sami Yehia ,  Joydeep Ray

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/18 ,  G06F1/32

CPC classification number: G11C5/148 ,  G06F1/189 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3275 ,  Y02D10/14

Abstract: An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

公开(公告)号：US20190095554A1

公开(公告)日：2019-03-28

申请号：US15718110

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Su Wei Lim ,  Kuan Hua Tan ,  Prashanth Kalluraya

IPC: G06F17/50 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.

公开(公告)号：US09665155B2

公开(公告)日：2017-05-30

申请号：US14366177

申请日：2013-12-28

Applicant: Intel Corporation

Inventor： Uttam K. Sengupta ,  Rajasekaran Andiappan ,  Prashanth Kalluraya ,  Bruce L. Fleming

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/32 ,  G06F1/3243 ,  G06F9/5094 ,  Y02D10/22

Abstract: Methods and apparatus relating to increasing energy efficiency of sensor controllers are described. In an embodiment, logic (e.g., within a sensor controller) performs one or more tasks corresponding to acquisition of data from one or more sensors. The logic performs the one or more tasks to allow a processor core of the sensor controller to enter (or stay in) a low power consumption state during performance of the one or more data acquisition tasks. Other embodiments are also disclosed and claimed.

公开(公告)号：US09489322B2

公开(公告)日：2016-11-08

申请号：US14317308

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Prashanth Kalluraya

IPC: H03M13/00 ,  G06F13/16 ,  G06F13/42 ,  H04L1/18

CPC classification number: G06F13/1631 ,  G06F13/4234 ,  H04L1/1867

Abstract: In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，装置包括消耗逻辑，用于请求和处理包括关键数据部分和第二数据部分的数据，所述数据存储在耦合到插入在所述装置和所述存储器之间的处理器的存储器中。 此外，该装置包括耦合到消费逻辑的协议栈逻辑，以经由处理器向存储器发出读请求，以响应于读请求来请求数据并接收多个完成。 在一个实施例中，协议栈逻辑包括完成处理逻辑，用于在完成之后完成协议栈处理之前将第一个完成的数据发送到消费逻辑。 描述和要求保护其他实施例。