公开(公告)号：US20230091969A1

公开(公告)日：2023-03-23

申请号：US17483123

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Gaurav Porwal ,  Theodros Yigzaw ,  Subhankar Panda ,  John Holm

IPC: G06F11/07 ,  G06F13/40

Abstract: Methods and apparatus relating to lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors are described. In an embodiment, a plurality of storage entries store error information to be detected at one or more physical lanes of an interface. Faulty lane detection logic circuitry determines which of the one or more physical lanes is faulty or more likely to be faulty based at least in part on the stored error information for the one or more physical lanes of the interface. The stored error information comprises historical error details for the one or more physical lanes of the interface. Other embodiments are also disclosed and claimed.

公开(公告)号：US11182313B2

公开(公告)日：2021-11-23

申请号：US16424875

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Theodros Yigzaw

IPC: G06F12/00 ,  G06F13/16 ,  G06F12/0831 ,  G06F12/0868

Abstract: In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.

公开(公告)号：US11068339B2

公开(公告)日：2021-07-20

申请号：US16417555

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20190272214A1

公开(公告)日：2019-09-05

申请号：US16417555

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/10 ,  G06F11/07

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20160343453A1

公开(公告)日：2016-11-24

申请号：US15226863

申请日：2016-08-02

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

IPC: G11C29/36 ,  G11C29/18 ,  G11C29/44 ,  G11C29/38

CPC classification number: G11C29/36 ,  G11C29/18 ,  G11C29/38 ,  G11C29/44 ,  G11C29/56008

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

公开(公告)号：US20220196733A1

公开(公告)日：2022-06-23

申请号：US17131477

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Gaurav Porwal ,  Subhankar Panda ,  Theodros Yigzaw ,  John Holm

IPC: G01R31/317

Abstract: Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

公开(公告)号：US20200004633A1

公开(公告)日：2020-01-02

申请号：US16292085

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/14 ,  G06F11/10

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US20180349231A1

公开(公告)日：2018-12-06

申请号：US15610067

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Subhankar Panda ,  Sarathy Jayakumar ,  Gaurav Porwal ,  Theodros Yigzaw

IPC: G06F11/14

CPC classification number: G06F11/0793 ,  G06F11/0772 ,  G06F11/0796 ,  G06F11/1415 ,  G06F11/142 ,  G06F11/1441

Abstract: A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.

公开(公告)号：US20180095681A1

公开(公告)日：2018-04-05

申请号：US15282463

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert C. Swanson ,  Tony S. Baker ,  Theodros Yigzaw ,  Chris Ackles ,  Celeste M. Brown

IPC: G06F3/06 ,  G11C13/00

CPC classification number: G06F11/1417 ,  G06F11/0778 ,  G06F11/0787 ,  G11C13/0004

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to utilize non-volatile random access memory for information storage in response to error conditions are disclosed. Example methods disclosed herein include accessing, with a power control unit associated with a processor, first information describing available capacities of respective reserved regions of a plurality of non-volatile memory modules, the respective reserved regions of the non-volatile memory modules being separate from respective host-visible regions of the non-volatile memory modules. Disclosed example methods also include configuring, with the power control unit, an information storage architecture based on the first information. Disclosed example methods further include storing, with the power control unit, second information in one or more of the respective reserved regions of the non-volatile memory modules in accordance with the information storage architecture.

公开(公告)号：US20170344414A1

公开(公告)日：2017-11-30

申请号：US15168999

申请日：2016-05-31

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Theodros Yigzaw

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772

Abstract: In accordance with implementations disclosed herein, there is provided systems and methods for enabling error status and reporting in a machine check environment. A processing device includes an error status register and an error status component communicably coupled to the error status register. The error status component determines that a machine check error (MCE) is a first correctable error (CE) and sets a first error status corresponding to the first CE in the error status register based on a threshold value. The threshold value is based on a type of the first CE.