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    Creating, using, and managing protected cryptography keys
    1.
    发明授权
    Creating, using, and managing protected cryptography keys 有权

    公开(公告)号：US12261941B2

    公开(公告)日：2025-03-25

    申请号：US18040245

    申请日：2021-08-27

    Applicant: Intel Corporation

    Inventor： Jason W. Brandt ,  Steven L. Grobman ,  Vedvyas Shanbhogue

    IPC: H04L9/08 ,  H04L9/32

    Abstract: System, method, and apparatus embodiments for creating, using, and managing protected cryptography keys are described. In an embodiment, an apparatus includes a decoder, an execution unit, and a cache. The decoder is to decode a single instruction into a decoded single instruction, the single instruction having a first source operand to specify encrypted data and a second source operand to specify a handle including a first including ciphertext of an encryption key, an integrity tag, and additional authentication data. The execution unit is to execute the decoded single instruction to perform a first check of the integrity tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data, perform a second check of a current request against one or more restrictions specified by the additional authentication data of the handle, decrypt the ciphertext to generate an encryption key only when the first check indicates no modification to the ciphertext or the additional authentication data and the second check indicates the one or more restrictions are not violated, decrypt the encrypted data with the encryption key to generate unencrypted data, and provide the unencrypted data as a result of the single instruction. The cache is to store the handle, wherein only a portion of the integrity tag is to be used in a lookup of the handle.

    PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS
    2.
    发明申请
    PROCESSOR EXTENSIONS TO PROTECT STACKS DURING RING TRANSITIONS 有权

    公开(公告)号：US20250053641A1

    公开(公告)日：2025-02-13

    申请号：US18904854

    申请日：2024-10-02

    Applicant: Intel Corporation

    Inventor： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Barry E. Huntley ,  Baiju V. Patel ,  Deepak K. Gupta

    IPC: G06F21/52 ,  G06F3/06 ,  G06F9/30 ,  G06F9/46 ,  G06F12/14

    Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

    Compressed cache memory with decompress on fault
    4.
    发明授权
    Compressed cache memory with decompress on fault 有权

    公开(公告)号：US12130738B2

    公开(公告)日：2024-10-29

    申请号：US17130632

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Vedvyas Shanbhogue ,  Jayesh Gaur ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Utkarsh Kakaiya

    IPC: G06F12/0802 ,  H03M7/30

    CPC classification number: G06F12/0802 ,  H03M7/60 ,  G06F2212/401 ,  G06F2212/60

    Abstract: An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.

    CIRCUITRY AND METHODS FOR IMPLEMENTING A TRUSTED EXECUTION ENVIRONMENT SECURITY MANAGER
    5.
    发明公开
    CIRCUITRY AND METHODS FOR IMPLEMENTING A TRUSTED EXECUTION ENVIRONMENT SECURITY MANAGER 审中-公开

    公开(公告)号：US20240320322A1

    公开(公告)日：2024-09-26

    申请号：US18575836

    申请日：2021-12-20

    Applicant: Intel Corporation

    Inventor： Jiewen Yao ,  Vedvyas Shanbhogue ,  Ravi Sahita

    IPC: G06F21/53 ,  G06F21/64

    CPC classification number: G06F21/53 ,  G06F21/64

    Abstract: Systems, methods, and apparatuses for implementing a trusted execution environment security manager are described. In one example, hardware processor includes a hardware processor core comprising a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain, a coupling between the hardware processor core and an input/output device, and a secure startup service circuit separate from the trust domain manager to, in response to a request from the trust domain manager, generate a secure communication session between the trust domain manager and the input/output device.

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