公开(公告)号：US09921989B2

公开(公告)日：2018-03-20

申请号：US14707656

申请日：2015-05-08

Applicant: Intel Corporation

Inventor： Krishnakumar Ganapathy ,  Yen-Cheng Liu ,  Antonio Juan ,  Steven R. Page ,  Jeffrey D. Chamberlain ,  Pau Cabre ,  Bahaa Fahim ,  Gunnar Gaubatz

IPC: G06F13/00 ,  G06F13/40 ,  G06F15/78 ,  G06F13/42 ,  G06F9/44

CPC classification number: G06F13/4022 ,  G06F9/4411 ,  G06F13/4036 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/7825

Abstract: In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

公开(公告)号：US09405687B2

公开(公告)日：2016-08-02

申请号：US14070864

申请日：2013-11-04

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Samuel D. Strom ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Krishnakumar Ganapathy ,  Cesar Maldonado

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F12/0831 ,  G06F12/0884 ,  G06F2212/2542 ,  Y02D10/13

Abstract: In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括一个或多个核心和分布式缓存归属代理（包括与每个核心相关联的部分）。 每个部分包括高速缓存控制器，用于接收对数据的读取请求，并且响应于不存在于与高速缓存控制器相关联的高速缓冲存储器中的数据，向存储器控制器发出存储器请求以与 对归属代理的存储器请求，其中归属代理将从高速缓存控制器接收存储器请求并且为存储器请求保留条目。 描述和要求保护其他实施例。

公开(公告)号：US12086653B2

公开(公告)日：2024-09-10

申请号：US17134065

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jeff A. Huxel ,  Jeffrey G. Wiedemeier ,  James D. Allen ,  Arvind Raman ,  Krishnakumar Ganapathy

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F11/07 ,  G06F11/16 ,  G06F9/455

CPC classification number: G06F9/52 ,  G06F9/30101 ,  G06F9/3885 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/1629 ,  G06F11/1683 ,  G06F9/45558

Abstract: A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.