公开(公告)号：US20180033875A1

公开(公告)日：2018-02-01

申请号：US15719776

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/10 ,  H01L29/778

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

公开(公告)号：US10355112B2

公开(公告)日：2019-07-16

申请号：US15719776

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/778

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

公开(公告)号：US09806180B2

公开(公告)日：2017-10-31

申请号：US14558947

申请日：2014-12-03

Applicant: Intel Corporation

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/778

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

公开(公告)号：US10998405B2

公开(公告)日：2021-05-04

申请号：US15777650

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Paul A. Zimmerman ,  Ian A. Young ,  Wilman Tsai

IPC: H01L51/05 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  C01B32/182 ,  H01L29/739 ,  H01L23/532

Abstract: Molecular Graphene (MG) of a physical size and bonding character that render the molecule suitable as a channel material in an electronic device, such as a tunnel field effect transistor (TFET). The molecular graphene may be a large polycyclic aromatic hydrocarbon (PAH) employed as a discrete element, or as a repeat unit, within an active or passive electronic device. In some embodiments, a functionalized PAH is disposed over a substrate surface and extending between a plurality of through-substrate vias. Heterogeneous surfaces on the substrate are employed to direct deposition of the functionalized PAH molecule to surface sites interstitial to the array of vias. Vias may be backfilled with conductive material as self-aligned source/drain contacts. Directed self-assembly techniques may be employed to form local interconnect lines coupled to the conductive via material. In some embodiments, graphene-based interconnects comprising a linear array of PAH molecules are formed over a substrate.

公开(公告)号：US09899505B2

公开(公告)日：2018-02-20

申请号：US14597128

申请日：2015-01-14

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/225 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47

CPC classification number: H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

公开(公告)号：US20150084000A1

公开(公告)日：2015-03-26

申请号：US14558947

申请日：2014-12-03

Applicant: INTEL CORPORATION

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。 描述和要求保护其他实施例。