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    Inter-cluster shared data management in sub-NUMA cluster
    1.
    发明授权
    Inter-cluster shared data management in sub-NUMA cluster 有权

    公开(公告)号：US12210446B2

    公开(公告)日：2025-01-28

    申请号：US18284265

    申请日：2021-06-21

    Applicant: Intel Corporation

    Inventor： Zhe Wang ,  Lingxiang Xiang ,  Christopher J. Hughes

    IPC: G06F12/00 ,  G06F9/30 ,  G06F12/02 ,  G06F12/0811

    Abstract: An embodiment of an integrated circuit may comprise circuitry communicatively coupled to two or more sub-non-uniform memory access clusters (SNCs) to allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space. An embodiment of an apparatus may comprise decode circuitry to decode a single instruction, the single instruction to include a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to provide an indicated SNC memory allocation policy (e.g., a SNC policy hint). Other embodiments are disclosed and claimed.

    Processor instructions for data compression and decompression
    2.
    发明授权
    Processor instructions for data compression and decompression 有权

    公开(公告)号：US12106104B2

    公开(公告)日：2024-10-01

    申请号：US17133328

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Christopher J. Hughes

    IPC: G06F9/30 ,  G06F12/0862 ,  H03M7/30

    CPC classification number: G06F9/30047 ,  G06F9/30145 ,  G06F12/0862 ,  H03M7/30 ,  G06F2212/602

    Abstract: A processor that includes compression instructions to compress multiple adjacent data blocks of uncompressed read-only data stored in memory into one compressed read-only data block and store the compressed read-only data block in multiple adjacent blocks in the memory is provided. During execution of an application to operate on the read-only data, one of the multiple adjacent blocks storing the compressed read-only block is read from memory, stored in a prefetch buffer and decompressed in the memory controller. In response to a subsequent request during execution of the application for an adjacent data block in the compressed read-only data block, the uncompressed adjacent block is read directly from the prefetch buffer.

    Multi-level system memory with near memory scrubbing based on predicted far memory idle time
    4.
    发明授权
    Multi-level system memory with near memory scrubbing based on predicted far memory idle time 有权

    公开(公告)号：US10120806B2

    公开(公告)日：2018-11-06

    申请号：US15193952

    申请日：2016-06-27

    Applicant: INTEL CORPORATION

    Inventor： Zhe Wang ,  Christopher B. Wilkerson ,  Zeshan A. Chishti

    IPC: G06F12/00 ,  G06F12/0873 ,  G06F12/123 ,  G06F12/0804

    Abstract: An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory. The memory controller also includes idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory. The memory controller is to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that an observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory.

    DYNAMIC CACHE COHERENCE PROTOCOL BASED ON RUNTIME INTERCONNECT UTILIZATION
    5.
    发明公开
    DYNAMIC CACHE COHERENCE PROTOCOL BASED ON RUNTIME INTERCONNECT UTILIZATION 审中-公开

    公开(公告)号：US20240303195A1

    公开(公告)日：2024-09-12

    申请号：US18562743

    申请日：2021-12-15

    Applicant: Intel Corporation

    Inventor： Keqiang Wu ,  Lingxiang Xiang ,  Heidi Pan ,  Christopher J. Hughes ,  Zhe Wang

    IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0891

    CPC classification number: G06F12/0835 ,  G06F12/084 ,  G06F12/0891

    Abstract: In one embodiment, a processor includes interconnect circuitry, processing circuitry, a first cache, and cache controller circuitry. The interconnect circuitry communicates over a processor interconnect with a second processor that includes a second cache. The processing circuitry generates a memory read request for a corresponding memory address of a memory. Based on the memory read request, the cache controller circuitry detects a cache miss in the first cache, which indicates that the first cache does not contain a valid copy of data for the corresponding memory address. Based on the cache miss, the cache controller circuitry requests the data from the second cache or the memory based on a current bandwidth utilization of the processor interconnect.

    FRAME PACING FOR IMPROVED EXPERIENCES IN 3D APPLICATIONS
    7.
    发明申请
    FRAME PACING FOR IMPROVED EXPERIENCES IN 3D APPLICATIONS 有权

    公开(公告)号：US20220122566A1

    公开(公告)日：2022-04-21

    申请号：US17072694

    申请日：2020-10-16

    Applicant: Intel Corporation

    Inventor： Travis Schluessler ,  Thomas Petersen ,  Charles Moidel ,  Gary Smith ,  Zhe Wang ,  Rafal Rudnicki

    IPC: G09G5/18 ,  G06T1/60

    Abstract: Methods, systems and apparatuses may provide for technology that determines measured timing data in response to a presentation request from an application, wherein the measured timing data is associated with one or more previous frames and the presentation request is associated with one or more subsequent frames. The technology may also determine scheduling times for the subsequent frame(s) based on the measured timing data, wherein the scheduling times include a simulation time, a rendering time, a driver submission time, a hardware submission time, and a display time. In one example, the technology controls a pacing of the subsequent frame(s) on a display in accordance with the scheduling times.

    Caching bypass mechanism for a multi-level memory
    8.
    发明授权
    Caching bypass mechanism for a multi-level memory 有权

    公开(公告)号：US11055228B2

    公开(公告)日：2021-07-06

    申请号：US16264615

    申请日：2019-01-31

    Applicant: Intel Corporation

    Inventor： Wei Wu ,  Zhe Wang

    IPC: G06F12/08 ,  G06F12/0888

    Abstract: An apparatus is described. The apparatus includes memory controller logic circuitry to interface to a multi-level memory having a higher memory level to act as a memory side cache for a lower memory level. The memory controller logic circuitry having policy determination circuitry to prevent lesser accessed data items from occupying space in the higher memory level at the expense of more frequently accessed data items.

    Cache architecture using way ID to reduce near memory traffic in a two-level memory system
    9.
    发明授权
    Cache architecture using way ID to reduce near memory traffic in a two-level memory system 有权

    公开(公告)号：US10884927B2

    公开(公告)日：2021-01-05

    申请号：US15927715

    申请日：2018-03-21

    Applicant: Intel Corporation

    Inventor： Zhe Wang ,  Alaa R. Alameldeen

    IPC: G06F12/0811 ,  G06F12/0804

    Abstract: One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.

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