公开(公告)号：US09974024B2

公开(公告)日：2018-05-15

申请号：US15077197

申请日：2016-03-22

Applicant: Intel IP Corporation

Inventor： Michael Speth ,  Armin Haeutle ,  Frank Huertgen ,  Biswajit Dey ,  Markus Jordan

IPC: H04W52/02

CPC classification number: H04W52/0245 ,  H04W52/0229 ,  Y02D70/00 ,  Y02D70/1242 ,  Y02D70/1244 ,  Y02D70/1262

Abstract: A circuit according to an example includes a receiver circuit configured to receive a signal including a data stream, the data stream including at least one block of data, a block of the at least one block of data including at least two sub-blocks, a payload of the block being redundantly encoded in the at least two sub-blocks, and the at least two sub-blocks of the block being consistently arranged over time inside the block. The circuit further includes a control circuit configured to switch the receiver circuit into a non-ready-to-receive state during at least a part of at least one of the at least two sub-blocks of the block, when an enable condition is fulfilled.

公开(公告)号：US20160277174A1

公开(公告)日：2016-09-22

申请号：US15042252

申请日：2016-02-12

Applicant: Intel IP Corporation

Inventor： Admir Burnic ,  Frank Huertgen

IPC: H04L7/00 ,  H04W88/06 ,  H04B1/3816

CPC classification number: H04L7/0008 ,  H04B1/3816 ,  H04W56/001 ,  H04W56/0035 ,  H04W88/06

Abstract: A synchronization device includes a receiver circuit configured to receive data from a first radio network during a first time interval and to receive data from a second radio network during a second time interval; a frequency synchronization circuit configured to control a common system clock based on first data received from the first radio network and based on second data received from the second radio network; and a timing synchronization circuit configured to time-synchronize data reception based on the common system clock and based on a free running clock.

Abstract translation: 同步装置包括被配置为在第一时间间隔期间从第一无线电网络接收数据并且在第二时间间隔期间从第二无线电网络接收数据的接收机电路; 频率同步电路，被配置为基于从第一无线电网络接收的第一数据并且基于从第二无线电网络接收的第二数据来控制公共系统时钟; 以及定时同步电路，被配置为基于公共系统时钟并基于自由运行时钟来对数据接收进行时间同步。

公开(公告)号：US10285118B2

公开(公告)日：2019-05-07

申请号：US15357751

申请日：2016-11-21

Applicant: INTEL IP CORPORATION

Inventor： Umer Salim ,  Tudor Murgan ,  Thorsten Clevorn ,  Herbert Dawid ,  Jean-Xavier Canonici ,  Frank Huertgen ,  Peter Ascheuer ,  Almansor Kerroum ,  Sonja Stefan-Vetten

IPC: H04W36/00 ,  H04W36/24 ,  H04W36/30 ,  H04W36/32 ,  H04W48/04 ,  H04W48/16 ,  H04W84/04

Abstract: According to an example, a communication terminal is described comprising a determiner configured to determine cell search control information including at least a radio access technology to be searched for, a search duration, a number of search iterations, a number of antennas to be used for the search and based on at least one of information about the current radio conditions that the communication terminal is experiencing, position of the terminal, historical information about the presence of the radio cells at the position of the communication terminal, communication terminal attach history in terms of moving from some specific RATs/cells to other specific RATs/cells, proximity sensors' information and a transceiver configured to perform a cell search based on the determined cell search control information.

公开(公告)号：US10122522B2

公开(公告)日：2018-11-06

申请号：US15042252

申请日：2016-02-12

Applicant: Intel IP Corporation

Inventor： Admir Burnic ,  Frank Huertgen

IPC: H04W88/06 ,  H04L7/00 ,  H04B1/3816 ,  H04W56/00

Abstract: A synchronization device includes a receiver circuit configured to receive data from a first radio network during a first time interval and to receive data from a second radio network during a second time interval; a frequency synchronization circuit configured to control a common system clock based on first data received from the first radio network and based on second data received from the second radio network; and a timing synchronization circuit configured to time-synchronize data reception based on the common system clock and based on a free running clock.

公开(公告)号：US20160316434A1

公开(公告)日：2016-10-27

申请号：US15077197

申请日：2016-03-22

Applicant: Intel IP Corporation

Inventor： Michael Speth ,  Armin Haeutle ,  Frank Huertgen ,  Biswajit Dey ,  Markus Jordan

IPC: H04W52/02 ,  H04W24/08

CPC classification number: H04W52/0245 ,  H04W52/0229 ,  Y02D70/00 ,  Y02D70/1242 ,  Y02D70/1244 ,  Y02D70/1262

Abstract: A circuit according to an example includes a receiver circuit configured to receive a signal including a data stream, the data stream including at least one block of data, a block of the at least one block of data including at least two sub-blocks, a payload of the block being redundantly encoded in the at least two sub-blocks, and the at least two sub-blocks of the block being consistently arranged over time inside the block. The circuit further includes a control circuit configured to switch the receiver circuit into a non-ready-to-receive state during at least a part of at least one of the at least two sub-blocks of the block, when an enable condition is fulfilled.

Abstract translation: 根据示例的电路包括被配置为接收包括数据流的信号的接收器电路，所述数据流包括至少一个数据块，所述至少一个数据块的块包括至少两个子块， 所述块的有效载荷被冗余地编码在所述至少两个子块中，并且所述块的所述至少两个子块在所述块内随时间一致地排列。 该电路还包括控制电路，该控制电路被配置为当满足该允许条件时，在该块的至少两个子块中的至少一个子块的至少一部分期间将接收器电路切换为不准备接收状态 。