公开(公告)号：US08823415B2

公开(公告)日：2014-09-02

申请号：US13645493

申请日：2012-10-04

Applicant: Industrial Technology Research Institute

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Yu-Sheng Chen ,  Zhe-Hui Lin

IPC: H03K19/20 ,  H01L23/522

CPC classification number: H03K19/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H03K19/02 ,  H01L2924/00

Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.

Abstract translation: 提供了包括第一电阻性非易失性存储器件和第二电阻性非易失性存储器件的逻辑门。 当第一和第二电阻性非易失性存储器件的顶部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的底部电极分别耦合到第一输入端和 逻辑门的第二输入端。 当第一和第二电阻性非易失性存储器件的底部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的顶电极分别耦合到第一输入端 和逻辑门的第二个输入端。

公开(公告)号：US20140115243A1

公开(公告)日：2014-04-24

申请号：US13974001

申请日：2013-08-22

Applicant: Industrial Technology Research Institute

Inventor： Chih-He Lin ,  Sih-Han Li ,  Wen-Pin Lin ,  Shyh-Shyuan Sheu

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

Abstract: A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.

Abstract translation: 电阻式随机存取存储器件包括存储器阵列，读取电路，回写逻辑电路和回写电路。 读取电路读取存储在所选择的存储器单元中的数据，并且相应地产生第一控制信号。 回写逻辑电路根据第一控制信号和第二控制信号产生回写控制信号。 回写电路根据回写控制信号和回写电压对所选择的存储单元执行写回操作，以将所选存储单元的电阻状态从低电阻状态改变为 并且根据所选存储单元的电阻状态产生第二控制信号。

公开(公告)号：US09378785B2

公开(公告)日：2016-06-28

申请号：US13974001

申请日：2013-08-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chih-He Lin ,  Sih-Han Li ,  Wen-Pin Lin ,  Shyh-Shyuan Sheu

IPC: G11C11/00 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C7/1072 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

Abstract: A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.

Abstract translation: 电阻式随机存取存储器件包括存储器阵列，读取电路，回写逻辑电路和回写电路。 读取电路读取存储在所选择的存储器单元中的数据，并且相应地产生第一控制信号。 回写逻辑电路根据第一控制信号和第二控制信号产生回写控制信号。 回写电路根据回写控制信号和回写电压对所选择的存储单元执行写回操作，以将所选存储单元的电阻状态从低电阻状态改变为 并且根据所选存储单元的电阻状态产生第二控制信号。

公开(公告)号：US20140035620A1

公开(公告)日：2014-02-06

申请号：US13645493

申请日：2012-10-04

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Yu-Sheng Chen ,  Zhe-Hui Lin

IPC: H03K19/20

CPC classification number: H03K19/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H03K19/02 ,  H01L2924/00

Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.

Abstract translation: 提供了包括第一电阻性非易失性存储器件和第二电阻性非易失性存储器件的逻辑门。 当第一和第二电阻性非易失性存储器件的顶部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的底部电极分别耦合到第一输入端和 逻辑门的第二输入端。 当第一和第二电阻性非易失性存储器件的底部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的顶电极分别耦合到第一输入端 和逻辑门的第二输入端。

公开(公告)号：US08872543B2

公开(公告)日：2014-10-28

申请号：US13872168

申请日：2013-04-29

Applicant: Industrial Technology Research Institute

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Shyh-Shyuan Sheu ,  Hsin-Chi Lai

IPC: H03K19/173 ,  G06F7/38 ,  H03K19/177

CPC classification number: H03K19/1776

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract translation: 提供了可配置逻辑块（CLB）和CLB的操作方法。 CLB包括存储单元和选择电路。 存储单元包括第一电阻性非易失性存储器（RNVM）元件和第二RNVM元件。 第一和第二RNVM元件的顶部电极（TE）耦合到存储器单元的输出端子。 第一和第二RNVM元件的底部电极（BE）分别耦合到存储器单元的第一偏置端子和第二偏置端子。 选择电路根据输入逻辑值选择一个存储器单元，并根据所选存储器单元的输出逻辑值确定CLB的输出逻辑值。

公开(公告)号：US20140210514A1

公开(公告)日：2014-07-31

申请号：US13872168

申请日：2013-04-29

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Shyh-Shyuan Sheu ,  Hsin-Chi Lai

IPC: H03K19/177

CPC classification number: H03K19/1776

Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract translation: 提供了可配置逻辑块（CLB）和CLB的操作方法。 CLB包括存储单元和选择电路。 存储单元包括第一电阻性非易失性存储器（RNVM）元件和第二RNVM元件。 第一和第二RNVM元件的顶部电极（TE）耦合到存储器单元的输出端子。 第一和第二RNVM元件的底部电极（BE）分别耦合到存储器单元的第一偏置端子和第二偏置端子。 选择电路根据输入逻辑值选择一个存储器单元，并根据所选存储器单元的输出逻辑值确定CLB的输出逻辑值。