公开(公告)号：US09076771B2

公开(公告)日：2015-07-07

申请号：US13974909

申请日：2013-08-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sih-Han Li ,  Pei-Ling Tseng ,  Zhe-Hui Lin ,  Chih-Sheng Lin

IPC: H01L29/93 ,  H01L23/48 ,  H01L27/08 ,  H01L29/94

CPC classification number: H01L23/481 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.

Abstract translation: 提供变容二极管。 衬底包括衬底中的第一表面，第二表面和第一开口以及第二开口。 导电材料填充第一和第二开口，以形成第一贯穿晶片通孔（TWV）和第二通晶片通孔。 第一电容器耦合在第一通晶片通孔和第一端子之间。 第二电容器耦合在第二通晶片通孔和第二端子之间。 第一贯穿晶片通孔和第二贯通晶片通孔之间的耗尽区电容器的电容由施加到第一贯穿晶片通孔和第二贯通晶片通孔的偏置电压决定。

公开(公告)号：US20140035620A1

公开(公告)日：2014-02-06

申请号：US13645493

申请日：2012-10-04

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Yu-Sheng Chen ,  Zhe-Hui Lin

IPC: H03K19/20

CPC classification number: H03K19/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H03K19/02 ,  H01L2924/00

Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.

Abstract translation: 提供了包括第一电阻性非易失性存储器件和第二电阻性非易失性存储器件的逻辑门。 当第一和第二电阻性非易失性存储器件的顶部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的底部电极分别耦合到第一输入端和 逻辑门的第二输入端。 当第一和第二电阻性非易失性存储器件的底部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的顶电极分别耦合到第一输入端 和逻辑门的第二输入端。

公开(公告)号：US08823415B2

公开(公告)日：2014-09-02

申请号：US13645493

申请日：2012-10-04

Applicant: Industrial Technology Research Institute

Inventor： Wen-Pin Lin ,  Chih-He Lin ,  Yu-Sheng Chen ,  Zhe-Hui Lin

IPC: H03K19/20 ,  H01L23/522

CPC classification number: H03K19/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H03K19/02 ,  H01L2924/00

Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.

Abstract translation: 提供了包括第一电阻性非易失性存储器件和第二电阻性非易失性存储器件的逻辑门。 当第一和第二电阻性非易失性存储器件的顶部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的底部电极分别耦合到第一输入端和 逻辑门的第二输入端。 当第一和第二电阻性非易失性存储器件的底部电极耦合到逻辑门的输出端时，第一和第二电阻性非易失性存储器件的顶电极分别耦合到第一输入端 和逻辑门的第二个输入端。

公开(公告)号：US20140175606A1

公开(公告)日：2014-06-26

申请号：US13974909

申请日：2013-08-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sih-Han Li ,  Pei-Ling Tseng ,  Zhe-Hui Lin ,  Chih-Sheng Lin

IPC: H01L49/02

CPC classification number: H01L23/481 ,  H01L27/0808 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.

Abstract translation: 提供变容二极管。 衬底包括衬底中的第一表面，第二表面和第一开口以及第二开口。 导电材料填充第一和第二开口，以形成第一贯穿晶片通孔（TWV）和第二通晶片通孔。 第一电容器耦合在第一通晶片通孔和第一端子之间。 第二电容器耦合在第二通晶片通孔和第二端子之间。 第一贯穿晶片通孔和第二贯通晶片通孔之间的耗尽区电容器的电容由施加到第一贯穿晶片通孔和第二贯通晶片通孔的偏置电压决定。

公开(公告)号：US08942027B1

公开(公告)日：2015-01-27

申请号：US13939062

申请日：2013-07-10

Applicant: Industrial Technology Research Institute

Inventor： Ching-Hao Chuang ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Zhe-Hui Lin

IPC: G11C11/00 ,  G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081

Abstract: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node.

Abstract translation: 存储器存储电路包括易失性存储器部分，控制部分和非易失性存储器部分。 易失性存储器部分包括存储一对互补逻辑数据的第一节点和第二节点。 控制部分包括第一晶体管和第二晶体管。 第一晶体管和第二晶体管的栅电极被耦合以接收存储信号，并且第一和第二晶体管的第一电极被耦合以接收控制信号。 非易失性存储器部分包括第一电阻存储器元件和第二电阻存储元件，用于存储该对互补逻辑数据。 第一电阻性存储元件耦合在第一晶体管的第二电极和第一节点之间，而第二电阻存储元件耦合在第二晶体管的第二电极和第二节点之间。

公开(公告)号：US20150016176A1

公开(公告)日：2015-01-15

申请号：US13939062

申请日：2013-07-10

Applicant: Industrial Technology Research Institute

Inventor： Ching-Hao Chuang ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Zhe-Hui Lin

IPC: G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081

Abstract: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node.

Abstract translation: 存储器存储电路包括易失性存储器部分，控制部分和非易失性存储器部分。 易失性存储器部分包括存储一对互补逻辑数据的第一节点和第二节点。 控制部分包括第一晶体管和第二晶体管。 第一晶体管和第二晶体管的栅电极被耦合以接收存储信号，并且第一和第二晶体管的第一电极被耦合以接收控制信号。 非易失性存储器部分包括第一电阻存储器元件和第二电阻存储元件，用于存储该对互补逻辑数据。 第一电阻性存储元件耦合在第一晶体管的第二电极和第一节点之间，而第二电阻存储元件耦合在第二晶体管的第二电极和第二节点之间。