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    Health monitoring of a circuit
    2.
    发明授权
    Health monitoring of a circuit 有权

    公开(公告)号：US10955464B2

    公开(公告)日：2021-03-23

    申请号：US15960911

    申请日：2018-04-24

    Applicant: Infineon Technologies AG

    Inventor： Vincenzo Fiore ,  Oliver Frank ,  Helmut Kollmann ,  Michael Platzer ,  Thomas Sailer ,  Jochen O. Schrattenecker

    IPC: G01R31/28 ,  G01R19/10

    Abstract: A method is disclosed use with a circuit device that includes a circuit having a predetermined voltage-current characteristic and a detector configured to detect a voltage-current relation of the circuit. The method includes using the detector to detect the voltage-current relation of the circuit, and indicating if the detected voltage-current relation differs from the predetermined voltage-current characteristic. A circuit device includes a circuit having a predetermined voltage-current characteristic, and a detector configured to detect a voltage-current relation of the circuit. The circuit device is configured to indicate if the detected voltage-current relation differs from the predetermined voltage-current characteristic.

    Clock monitoring for sequential logic circuits
    4.
    发明授权
    Clock monitoring for sequential logic circuits 有权
    时序监控用于顺序逻辑电路

    公开(公告)号：US09385700B2

    公开(公告)日：2016-07-05

    申请号：US14497360

    申请日：2014-09-26

    Applicant: Infineon Technologies AG

    Inventor： Klemens Kordik ,  Bernhard Gstoettenbauer ,  Klaus Buchner ,  Thomas Sailer

    IPC: H03K5/24 ,  H03K4/08

    CPC classification number: H03K5/24 ,  H03K4/08

    Abstract: A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.

    Abstract translation: 描述用于监视时钟信号的监视电路。 根据本公开的一个示例，监视电路包括脉冲发生器和比较器电路。 脉冲发生器被配置为产生与时钟信号同步的脉冲序列，其中每个脉冲具有单调上升或下降信号电平的边沿。 比较器电路接收脉冲序列，并被配置为在时钟信号的每个时钟周期内检测脉冲序列的信号电平是否在该时钟周期内的特定时刻在期望范围之外 时钟信号。

    Clock Monitoring for Sequential Logic Circuits
    5.
    发明申请
    Clock Monitoring for Sequential Logic Circuits 有权
    顺序逻辑电路的时钟监控

    公开(公告)号：US20160094212A1

    公开(公告)日：2016-03-31

    申请号：US14497360

    申请日：2014-09-26

    Applicant: Infineon Technologies AG

    Inventor： Klemens Kordik ,  Bernhard Gstoettenbauer ,  Klaus Buchner ,  Thomas Sailer

    IPC: H03K5/24 ,  H03K4/08

    CPC classification number: H03K5/24 ,  H03K4/08

    Abstract: A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.

    Abstract translation: 描述用于监视时钟信号的监视电路。 根据本公开的一个示例，监视电路包括脉冲发生器和比较器电路。 脉冲发生器被配置为产生与时钟信号同步的脉冲序列，其中每个脉冲具有单调上升或下降信号电平的边沿。 比较器电路接收脉冲序列，并且被配置为在时钟信号的每个时钟周期内检测脉冲序列的信号电平是否在该时钟周期内的特定时刻在期望范围之外 时钟信号。

    Combined lock/out-of-lock detector for phase locked loops
    7.
    发明授权
    Combined lock/out-of-lock detector for phase locked loops 有权
    用于锁相环的组合锁/失锁检测器

    公开(公告)号：US09258000B1

    公开(公告)日：2016-02-09

    申请号：US14493539

    申请日：2014-09-23

    Applicant: Infineon Technologies AG

    Inventor： Klemens Kordik ,  Thomas Sailer ,  Rainer Stuhlberger

    IPC: H03L7/095

    CPC classification number: H03L7/095 ,  H03L7/193

    Abstract: A detector for detecting a locked state and an out-of-lock state of a phase locked loop includes an out-of-lock detector circuit that receives a reference signal and an input signal representing a PLL oscillator signal. The out-of-lock detector detects an out-of-lock state of the PLL and generates an out-of-lock signal indicating whether an out-of-lock state is detected. The detector further includes a lock detector circuit that receives the reference signal and the input signal, detects a locked state of the PLL, and generates a lock signal indicating whether a locked state is detected. A logic circuit receives both the out-of-lock signal and the lock signal and combines both signals to obtain an output signal indicative of whether the PLL is in a locked state or an out-of-lock state.

    Abstract translation: 用于检测锁相环的锁定状态和失锁状态的检测器包括接收参考信号和表示PLL振荡器信号的输入信号的失锁检测器电路。 失锁检测器检测到PLL的失锁状态，并产生指示是否检测到失锁状态的失锁信号。 检测器还包括锁定检测器电路，其接收参考信号和输入信号，检测PLL的锁定状态，并产生指示是否检测到锁定状态的锁定信号。 逻辑电路接收失锁信号和锁定信号，并且组合两个信号以获得指示PLL是处于锁定状态还是处于非锁定状态的输出信号。

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