公开(公告)号：US20170288019A1

公开(公告)日：2017-10-05

申请号：US15626018

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Jessica S. KACHIAN ,  Marc C. FRENCH ,  Aaron A. BUDREVICH

IPC: H01L29/06

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

公开(公告)号：US20190237466A1

公开(公告)日：2019-08-01

申请号：US16318361

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Patrick H. KEYS ,  Hei KAM ,  Rishabh MEHANDRU ,  Aaron A. BUDREVICH

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/167 ,  H01L29/43 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

Abstract: A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.

公开(公告)号：US20200211901A1

公开(公告)日：2020-07-02

申请号：US15752189

申请日：2015-09-17

Applicant: Intel Corporation

Inventor： Scott B. CLENDENNING ,  Marvin MITAN ,  Aaron A. BUDREVICH

IPC: H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods for doping a subfin region of a semiconductor fin structure include forming a fin on a substrate; forming an oxide material on the substrate and a portion of the fin that corresponds to a sub-fin region of the fin; forming a hard mask on a top-fin region of the fin that is disposed above the sub-fin region; exposing a surface of the sub-fin region by removing the oxide material from a surface of the sub-fin region and leaving a layer of the oxide material on the substrate; depositing a dopant material on the hard mask, the surface of the subfin region, and the layer of the oxide material on the substrate; and removing the hard mask from the top-fin region to expose a surface of the top-fin region. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed

公开(公告)号：US20170047401A1

公开(公告)日：2017-02-16

申请号：US15334112

申请日：2016-10-25

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Van H. LE ,  Ravi PILLARISETTY ,  Jessica S. KACHIAN ,  Marc C. FRENCH ,  Aaron A. BUDREVICH

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/167 ,  H01L29/66 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

Abstract translation: 在那里制造的半导体器件堆叠和器件具有富锗器件层。 富锗器件层设置在衬底上方，其间布置有p型掺杂Ge蚀刻抑制层（例如，p型SiGe），以在去除牺牲半导体层期间抑制富锗器件层的蚀刻 Si比设备层更丰富。 随着在半导体膜堆叠中引入掩埋的p型掺杂半导体层，可以显着降低Ge在湿蚀刻剂（例如氢氧化物水溶液）中的溶解速率，从而提高蚀刻剂对Ge富集器件层的选择性。