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公开(公告)号：US12212351B2
公开(公告)日：2025-01-28
申请号：US17131872
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Ritesh A. Bhat , Steven Callender , Brent R. Carlton , Christopher D. Hull , Stefano Pellerano , Mustafijur Rahman , Peter Sagazio , Woorim Shin
IPC: H04B1/04
Abstract: Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.
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公开(公告)号：US11469709B2
公开(公告)日：2022-10-11
申请号：US17129483
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Stefano Pellerano , Christopher Hull
Abstract: A biasing scheme for a frequency multiplication circuit, and transceiver using LO signals provided by the frequency multiplication circuit are described. A frequency doubler is cascaded with a mixer to provide a mm-wave oscillator signal. The combination provides a frequency triple that of the LO frequency supplied to the frequency doubler from a PLL. A small-sized replica of the frequency doubler is used to determine biasing of transconductance devices of the frequency doubler. A voltage output of the replica is amplified and the difference between the output and a reference voltage is supplied as feedback to the control terminal of the transconductance devices to bias the transconductance devices to near threshold. The biasing is replicated at the frequency doubler to compensate for PVT variations. A PTAT current source tied to the output of the replica regulates an average output current of the frequency multiplication circuit.
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公开(公告)号：US10025363B2
公开(公告)日：2018-07-17
申请号：US14568836
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Thyagarajan Srinivasan
Abstract: The present disclosure is directed to device-agnostic power monitoring and profiling. A target device may be supplied with power through a power monitor that may generate power data based on the power provided to the target device and also transmit the power data. A diagnostic module in the target device may receive the power data and operational data regarding the target device. The diagnostic module may transmit at least one of the power data or the operational data to another device for processing, or may undertake processing the power and operational data. Processing the power and operational data may include generating relevant data by parsing the power and operational data and may then correlate the relevant power data with the relevant operational data. At least the correlated data may then be presented by the target device, may be made available via the Internet and/or may be transmitted to another device.
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公开(公告)号：US20220200532A1
公开(公告)日：2022-06-23
申请号：US17129483
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Stefano Pellerano , Christopher Hull
Abstract: A biasing scheme for a frequency multiplication circuit, and transceiver using LO signals provided by the frequency multiplication circuit are described. A frequency doubler is cascaded with a mixer to provide a mm-wave oscillator signal. The combination provides a frequency triple that of the LO frequency supplied to the frequency doubler from a PLL. A small-sized replica of the frequency doubler is used to determine biasing of transconductance devices of the frequency doubler. A voltage output of the replica is amplified and the difference between the output and a reference voltage is supplied as feedback to the control terminal of the transconductance devices to bias the transconductance devices to near threshold. The biasing is replicated at the frequency doubler to compensate for PVT variations. A PTAT current source tied to the output of the replica regulates an average output current of the frequency multiplication circuit.
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公开(公告)号：US20200083892A1
公开(公告)日：2020-03-12
申请号：US16126722
申请日：2018-09-10
Applicant: Intel Corporation
Inventor： Somnath Kundu , Stefano Pellerano , Abhishek Agrawal
Abstract: A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage.
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Patent Agency Ranking
公开(公告)号：US20200007116A1
公开(公告)日：2020-01-02
申请号：US16025148
申请日：2018-07-02
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Stefano Pellerano , Yanjie Wang , Peter Sagazio
Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.
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公开(公告)号：US11277143B1
公开(公告)日：2022-03-15
申请号：US17024419
申请日：2020-09-17
Applicant: Intel Corporation
Inventor： Somnath Kundu , Abhishek Agrawal , Brent Carlton
Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.
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公开(公告)号：US20220085822A1
公开(公告)日：2022-03-17
申请号：US17024419
申请日：2020-09-17
Applicant: Intel Corporation
Inventor： Somnath Kundu , Abhishek Agrawal , Brent Carlton
Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.
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公开(公告)号：US20200295765A1
公开(公告)日：2020-09-17
申请号：US16352043
申请日：2019-03-13
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Alon Cohen , Gil Horovitz , Somnath Kundu , Run Levinger , Stefano Pellerano , Jahnavi Sharma , Evgeny Shumaker , Izhak Hod
Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.
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公开(公告)号：US10594309B2
公开(公告)日：2020-03-17
申请号：US16025148
申请日：2018-07-02
Applicant: Intel Corporation
Inventor： Abhishek Agrawal , Stefano Pellerano , Yanjie Wang , Peter Sagazio
Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.
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