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    REDUCED WAKE UP DELAY FOR ON-DIE ROUTERS
    2.
    发明申请
    REDUCED WAKE UP DELAY FOR ON-DIE ROUTERS 审中-公开
    减少唤醒延迟线路路由器

    公开(公告)号：US20160164689A1

    公开(公告)日：2016-06-09

    申请号：US15012181

    申请日：2016-02-01

    Applicant: Intel Corporation

    Inventor： Dongkook Park ,  Akhilesh Kumar ,  Donglai Dai

    IPC: H04L12/12 ,  G06F1/32

    CPC classification number: H04L12/12 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3246 ,  G06F1/3253 ,  H03K19/0008 ,  H03K19/0016 ,  Y02B70/12 ,  Y02B70/30 ,  Y02D10/151

    Abstract: Techniques for power gating. A first on-die router has an output port to receive data from a switching fabric. The output port is placed in a power-gated state if there is no activity in the output port for a current cycle and no messages are to be received by the output port during a subsequent cycle. A second on-die router has an input port coupled with the output port of the first on-die router. The input port is placed in a power-gated state if an input port buffer is empty and the output port is not active. Power-gating of the input port and the output port are independent of each other.

    Abstract translation: 电力门控技术 第一个片上路由器具有从交换结构接收数据的输出端口。 如果在当前周期的输出端口中没有活动，并且在后续周期期间输出端口不接收消息，则输出端口处于电源门控状态。 第二个管芯路由器具有与第一管芯路由器的输出端口耦合的输入端口。 如果输入端口缓冲区为空并且输出端口未激活，则输入端口处于电源门控状态。 输入端口和输出端口的电源门控彼此独立。

    Flexible cache allocation technology priority-based cache line eviction algorithm
    3.
    发明授权
    Flexible cache allocation technology priority-based cache line eviction algorithm 有权

    公开(公告)号：US11656997B2

    公开(公告)日：2023-05-23

    申请号：US16696548

    申请日：2019-11-26

    Applicant: Intel Corporation

    Inventor： Neha Gholkar ,  Akhilesh Kumar

    IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/121

    CPC classification number: G06F12/0891 ,  G06F12/121 ,  G06F2212/1044 ,  G06F2212/60

    Abstract: Disclosed embodiments relate to a cache line eviction algorithm. In one example, a system includes a last level cache (LLC) having multiple ways, each allocated to one of multiple priorities, each having specified minimum and maximum ways to occupy, a cache control circuit (CCC) to store an incoming cache line (CL) having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.

    Device, system and method for coupling a network-on-chip with PHY circuitry
    4.
    发明授权
    Device, system and method for coupling a network-on-chip with PHY circuitry 有权

    公开(公告)号：US11134030B2

    公开(公告)日：2021-09-28

    申请号：US16542922

    申请日：2019-08-16

    Applicant: Intel Corporation

    Inventor： Akhilesh Kumar ,  Surhud Khare

    IPC: H04J3/06 ,  H04L12/933 ,  H04L12/715 ,  H04L12/773 ,  G06F15/78

    Abstract: Techniques and mechanisms for interconnecting network circuitry of an integrated circuit (IC) die and physical layer (PHY) circuits of the same IC die. In an embodiment, nodes of the network circuitry include first routers and processor cores, where the first routers are coupled to one another in an array configuration which includes rows and columns. First interconnects each extend to couple both to a corresponding one of the PHY circuits and to a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. In another embodiment, the network circuitry comprises network clusters which each include a different respective row of the array configuration.

    Reduced wake up delay for on-die routers
    6.
    发明授权
    Reduced wake up delay for on-die routers 有权
    降低了片上路由器的唤醒延迟

    公开(公告)号：US09250679B2

    公开(公告)日：2016-02-02

    申请号：US13791574

    申请日：2013-03-08

    Applicant: Intel Corporation

    Inventor： Dongkook Park ,  Akhilesh Kumar ,  Donglai Dai

    IPC: H04L12/28 ,  G06F1/32 ,  H03K19/00 ,  H04J1/16

    CPC classification number: H04L12/12 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3246 ,  G06F1/3253 ,  H03K19/0008 ,  H03K19/0016 ,  Y02B70/12 ,  Y02B70/30 ,  Y02D10/151

    Abstract: Techniques for power gating. A first on-die router has an output port to receive data from a switching fabric. The output port is placed in a power-gated state if there is no activity in the output port for a current cycle and no messages are to be received by the output port during a subsequent cycle. A second on-die router has an input port coupled with the output port of the first on-die router. The input port is placed in a power-gated state if an input port buffer is empty and the output port is not active. Power-gating of the input port and the output port are independent of each other.

    Abstract translation: 电力门控技术 第一个片上路由器具有从交换结构接收数据的输出端口。 如果在当前周期的输出端口中没有活动，并且在后续周期期间输出端口不接收消息，则输出端口处于电源门控状态。 第二个管芯路由器具有与第一管芯路由器的输出端口耦合的输入端口。 如果输入端口缓冲区为空并且输出端口未激活，则输入端口处于电源门控状态。 输入端口和输出端口的电源门控彼此独立。

    Flexible cache allocation technology priority-based cache line eviction algorithm
    7.
    发明授权
    Flexible cache allocation technology priority-based cache line eviction algorithm 有权

    公开(公告)号：US12182025B2

    公开(公告)日：2024-12-31

    申请号：US18321603

    申请日：2023-05-22

    Applicant: Intel Corporation

    Inventor： Neha Gholkar ,  Akhilesh Kumar

    IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/121

    Abstract: Disclosed embodiments relate to a cache line eviction algorithm. In one example, a system includes a last level cache (LLC) having multiple ways, each allocated to one of multiple priorities, each having specified minimum and maximum ways to occupy, a cache control circuit (CCC) to store an incoming cache line (CL) having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.

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