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    A SCALABLE POLYLITHIC ON-PACKAGE INTEGRATABLE APPARATUS AND METHOD
    2.
    发明申请
    A SCALABLE POLYLITHIC ON-PACKAGE INTEGRATABLE APPARATUS AND METHOD 有权

    公开(公告)号：US20230110247A1

    公开(公告)日：2023-04-13

    申请号：US17977236

    申请日：2022-10-31

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Shekhar Y. Borkar

    IPC: H01L23/532 ,  H01L21/78

    Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

    Architecture For On-Die Interconnect
    3.
    发明申请
    Architecture For On-Die Interconnect 审中-公开
    架构互连

    公开(公告)号：US20160173413A1

    公开(公告)日：2016-06-16

    申请号：US15042402

    申请日：2016-02-12

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Ankit More ,  Dinesh Somasekhar ,  David S. Dunning

    IPC: H04L12/933 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H04L49/109 ,  H01L23/5221 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，一种装置包括：配置在半导体管芯上的多个岛，多个岛中的每一个具有多个核; 以及多个网络交换机，其配置在所述半导体管芯上并且各自与所述多个岛中的一个岛相关联，其中每个网络交换机包括多个输出端口，所述输出端口的第一组各自耦合到相关联的网络交换机 经由点对点互连的岛屿和第二组输出端口各自经由点对多点互连耦合到多个岛的相关网络交换机。 描述和要求保护其他实施例。

    Device, system and method for coupling a network-on-chip with PHY circuitry
    4.
    发明授权
    Device, system and method for coupling a network-on-chip with PHY circuitry 有权

    公开(公告)号：US11134030B2

    公开(公告)日：2021-09-28

    申请号：US16542922

    申请日：2019-08-16

    Applicant: Intel Corporation

    Inventor： Akhilesh Kumar ,  Surhud Khare

    IPC: H04J3/06 ,  H04L12/933 ,  H04L12/715 ,  H04L12/773 ,  G06F15/78

    Abstract: Techniques and mechanisms for interconnecting network circuitry of an integrated circuit (IC) die and physical layer (PHY) circuits of the same IC die. In an embodiment, nodes of the network circuitry include first routers and processor cores, where the first routers are coupled to one another in an array configuration which includes rows and columns. First interconnects each extend to couple both to a corresponding one of the PHY circuits and to a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. In another embodiment, the network circuitry comprises network clusters which each include a different respective row of the array configuration.

    Scalable polylithic on-package integratable apparatus and method
    6.
    再颁专利
    Scalable polylithic on-package integratable apparatus and method 有权

    公开(公告)号：USRE49439E1

    公开(公告)日：2023-02-28

    申请号：US16703812

    申请日：2019-12-04

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Shekhar Y. Borkar

    IPC: H01L23/532 ,  H01L21/78

    Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

    INTEGRATED CIRCUIT DIE FOR EFFICIENT INCORPORATION IN A DIE STACK
    8.
    发明公开
    INTEGRATED CIRCUIT DIE FOR EFFICIENT INCORPORATION IN A DIE STACK 审中-公开

    公开(公告)号：US20230207428A1

    公开(公告)日：2023-06-29

    申请号：US17560915

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Shigeki Tomishima ,  Debendra Mallik

    IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L25/065

    CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657

    Abstract: Techniques and mechanisms for incorporating an integrated circuit (IC) die into a die stack. In an embodiment, the die comprises multiple interconnects extending vertically through the die. The multiple interconnects comprise first interconnects which participate in communications via a first channel, second interconnects which participate in communications via a second channel, and third interconnects which are locally insulated from any transmitter or receiver circuitry of the die. Along a direction within a horizontal plane, the third interconnects are in an alternating arrangement with the first interconnects and the second interconnects, wherein the first interconnects and the second interconnects are on opposite sides of a line which is orthogonal to the direction. In another embodiment, along the direction, the first interconnects are successively arranged to correspond to successively greater levels of bit significance, and the second interconnects are successively arranged to correspond to successively lesser levels of bit significance.

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