公开(公告)号：US20230401109A1

公开(公告)日：2023-12-14

申请号：US18237860

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Niall D. MCDONNELL ,  Ambalavanar ARULAMBALAM ,  Te Khac MA ,  Surekha PERI ,  Pravin PATHAK ,  James CLEE ,  An YAN ,  Steven POLLOCK ,  Bruce RICHARDSON ,  Vijaya Bhaskar KOMMINENI ,  Abhinandan GUJJAR

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5038

Abstract: Examples described herein relate to a load balancer that is configured to selectively perform ordering of requests from the one or more cores, allocate the requests into queue elements prior to allocation to one or more receiver cores of the one or more cores to process the requests, and perform two or more operations of: adjust a number of queues associated with a core of the one or more cores by changing a number of consumer queues (CQs) allocated to a single domain, adjust a number of target cores in a group of target cores to be load balanced, and order memory space writes from multiple caching agents (CAs).

公开(公告)号：US20240121194A1

公开(公告)日：2024-04-11

申请号：US18392028

申请日：2023-12-21

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Ambalavanar ARULAMBALAM ,  Bruce RICHARDSON ,  Te MA

IPC: H04L47/125 ,  H04L47/30 ,  H04L47/625

CPC classification number: H04L47/125 ,  H04L47/30 ,  H04L47/6255

Abstract: Methods, apparatus, and computer programs are disclosed for buffer management in load balancing. In one embodiment, a method is disclosed to comprise providing a set of buffers by a storage of a load balancer to store packets to be distributed by the load balancer, and distributing the packets by the load balancer to a set of cores of a computer processor to be processed by the set of cores. The method further comprises responsive to buffer utilization in the storage over a first threshold, obtaining by circuitry of the load balancer, from top of a memory stack coupled to the storage, additional buffers to store the packets to be distributed and responsive to buffer utilization in the storage below a second threshold, returning by the circuitry of the load balancer, available buffers in the storage to the top of the memory stack.

公开(公告)号：US20240334245A1

公开(公告)日：2024-10-03

申请号：US18737212

申请日：2024-06-07

Applicant: Intel Corporation

Inventor： John J. BROWNE ,  Andrey CHILIKIN ,  Elazar COHEN ,  Joseph HASTING ,  James CLEE ,  Jerry PIROG ,  Jamison D. WHITESELL ,  Ambalavanar ARULAMBALAM ,  Anjali Singhai JAIN ,  Andrew CUNNINGHAM ,  Ruben DAHAN

IPC: H04W28/06 ,  H04W28/02

CPC classification number: H04W28/06 ,  H04W28/0273 ,  H04W28/0289

Abstract: Examples described herein relate to a network interface device that performs: offloading processing of fragments of a packet to an accelerator; processing non-fragmented packets; and prioritizing dropping of fragments of the packet over dropping of non-fragmented packets. Offloading processing of fragments of the packet to the accelerator can include: the accelerator performing: reassembling the fragments of the packet into a first reassembly packet; and based on congestion associated with at least one of the fragments of the packet of the first reassembly packet: dropping fragments of the first reassembly packet associated with one or more flows; halting reassembly of the first reassembly packet; and forwarding a second packet to a host system, wherein the second packet indicates that congestion occurred, identifies one or more impacted flows, and indicates a number of dropped packet fragments.