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    CONFIGURABLE DEVICE INTERFACE
    3.
    发明申请
    CONFIGURABLE DEVICE INTERFACE 有权

    公开(公告)号：US20210232528A1

    公开(公告)日：2021-07-29

    申请号：US17208744

    申请日：2021-03-22

    Applicant: Intel Corporation

    Inventor： Patrick G. KUTCH ,  Andrey CHILIKIN ,  Jin YU ,  Cunming LIANG ,  Changpeng LIU ,  Ziye YANG ,  Gang CAO ,  Xiaodong LIU ,  Zhiguo WEN ,  Zhihua CHEN

    IPC: G06F13/40 ,  G06F9/445

    Abstract: Examples described herein relate to an apparatus comprising: a descriptor format translator accessible to a driver. In some examples, the driver and descriptor format translator share access to transmit and receive descriptors. In some examples, based on a format of a descriptor associated with a device differing from a second format of descriptor associated with the driver, the descriptor format translator is to: perform a translation of the descriptor from the format to the second format and store the translated descriptor in the second format for access by the device. In some examples, the device is to access the translated descriptor; the device is to modify content of the translated descriptor to identify at least one work request; and the descriptor format translator is to translate the modified translated descriptor into the format and store the translated modified translated descriptor for access by the driver.

    MEMORY ALLOCATION FOR DISTRIBUTED PROCESSING DEVICES
    6.
    发明申请
    MEMORY ALLOCATION FOR DISTRIBUTED PROCESSING DEVICES 有权

    公开(公告)号：US20210349820A1

    公开(公告)日：2021-11-11

    申请号：US15931476

    申请日：2020-05-13

    Applicant: Intel Corporation

    Inventor： Patrick G. KUTCH ,  Andrey CHILIKIN

    IPC: G06F12/0802 ,  G06F13/42

    Abstract: Examples described herein relate to an offload processor to receive data for transmission using a network interface or received in a packet by a network interface. In some examples, the offload processor can include a packet storage controller to determine whether to store data in a buffer of the offload processing device or a system memory after processing by the offload processing device. In some examples, determine whether to store data in a buffer of the offload processor or a system memory is based on one or more of: available buffer space, latency limit associated with the data, priority associated with the data, or available bandwidth through an interface between the buffer and the system memory. In some examples, the offload processor is to receive a descriptor and specify a storage location of data in the descriptor, wherein the storage location is within the buffer or the system memory.

    CONTROL PLANE ISOLATION
    9.
    发明申请
    CONTROL PLANE ISOLATION 有权

    公开(公告)号：US20220385534A1

    公开(公告)日：2022-12-01

    申请号：US17882317

    申请日：2022-08-05

    Applicant: Intel Corporation

    Inventor： Elazar COHEN ,  Keren GUY ,  Marina POPILOV ,  Andrey CHILIKIN

    IPC: H04L41/08 ,  H04L41/0894 ,  H04L41/0816

    Abstract: Examples described herein relate to a network interface device comprising circuitry and data plane circuitry. In some examples, the circuitry is to receive control configurations from multiple control planes and based on a management configuration, selectively deny a control configuration of the received control configurations to configure operations of the data plane circuitry. In some examples, selectively denying the control configuration comprises restrict different control planes from modification of configuration of the data plane circuitry

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