公开(公告)号：US09778902B2

公开(公告)日：2017-10-03

申请号：US13701374

申请日：2012-10-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Chengzhou Li ,  Albert Molina ,  Joseph H. Othmer ,  Steven C. Pinault ,  Meng-Lin Yu ,  Joseph Williams ,  Ramon Sanchez Perez ,  Jian-Guo Chen

IPC: G06F5/01 ,  G06F17/15 ,  G06F9/30 ,  H03H17/06 ,  H04B1/04 ,  H04L1/00 ,  H04L27/233 ,  H04B1/62 ,  H04L25/02 ,  H04L25/03 ,  H03M3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04L25/49 ,  H04B1/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.