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    Preamble detection using vector processors
    3.
    发明授权
    Preamble detection using vector processors 有权
    使用向量处理器的前导码检测

    公开(公告)号：US09184787B2

    公开(公告)日：2015-11-10

    申请号：US13800167

    申请日：2013-03-13

    Applicant: Intel Corporation

    Inventor： Meng-Lin Yu ,  Jian-Guo Chen ,  Alexander Alexandrovich Petyushko ,  Ivan Leonidovich Mazurenko

    IPC: H04B1/00 ,  H04B1/709 ,  H04B1/7113

    CPC classification number: H04B1/709 ,  H04B1/7113

    Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.

    Abstract translation: 在一个实施例中，可编程向量处理器在无线通信网络中执行前导码检测。 矢量处理器中的前导码检测的实现可以通过一组向量指令成为可能的，该矢量指令包括（i）用于加载接收数据的向量的循环加载指令，（ii）将接收到的数据的向量与 扰码以同时产生多个复相关，（iii）用于排列复数相关的向量的部分转置指令，供快速哈达马变换（FHT）处理器使用，以及（iv）用于对FHT处理执行FHT处理的FHT指令 复杂相关的向量。 在矢量处理器中实现前同步码检测允许更多的接收数据被同时处理。 结果，本公开的前导码检测器可以使用比使用硬件加速器实现的可比较的前同步码检测器更少的时钟周期来检测前导码。

    Vector processor having instruction set with sliding window non-linear convolutional function
    5.
    发明授权
    Vector processor having instruction set with sliding window non-linear convolutional function 有权
    矢量处理器具有滑动窗非线性卷积函数的指令集

    公开(公告)号：US09363068B2

    公开(公告)日：2016-06-07

    申请号：US14168615

    申请日：2014-01-30

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Joseph Williams ,  Meng-Lin Yu

    IPC: G06F17/15 ,  H04L5/14 ,  H04L25/08 ,  G06F17/50 ,  H04B1/62 ,  H04L1/00 ,  H04B1/04 ,  G06F9/30 ,  H04L25/03 ,  H04L27/36 ,  H04J11/00 ,  H04B1/525

    CPC classification number: H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

    Abstract: A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.

    Abstract translation: 提供具有具有滑动窗非线性卷积函数的指令集的处理器。 处理器获得对多个输入延迟信号样本执行非线性卷积函数的软件指令。 响应于用于非线性卷积函数的软件指令，处理器生成两个或更多个输入延迟信号样本的加权和，其中加权和包括被定义为一个或多个非线性卷积的和的多个可变系数， 输入延迟信号采样幅度的线性函数; 并重复所述生成步骤，用于输入延迟信号采样的至少一个时移版本，以计算多个连续输出。 用于非线性卷积函数的软件指令可选地是处理器的指令集的一部分。 非线性卷积函数可以对具有存储器的非线性系统进行建模，例如功率放大器模型和/或数字预失真功能。

    Apparatuses, methods, and systems for a user defined formatting instruction to configure multicast Benes network circuitry
    6.
    发明授权
    Apparatuses, methods, and systems for a user defined formatting instruction to configure multicast Benes network circuitry 有权

    公开(公告)号：US11334356B2

    公开(公告)日：2022-05-17

    申请号：US16457994

    申请日：2019-06-29

    Applicant: Intel Corporation

    Inventor： Jian-Guo Chen ,  David T. Dougherty ,  Steven Pinault ,  Parakalan Venkataraghavan ,  Joseph Williams ,  Meng-Lin Yu ,  Kamran Azadet

    IPC: G06F9/30 ,  H04L49/25 ,  H04L49/201 ,  G06F9/54

    Abstract: Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described. In one embodiment, a processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having fields that identify packed input data, packed control data, and a packed data destination; and an execution unit to execute the decoded single instruction to: send the packed control data to respective control inputs of a circuit that comprises an inverse butterfly circuit coupled in series to a butterfly circuit, wherein the inverse butterfly circuit comprises a first plurality of stages of multicast switches and the butterfly circuit comprises a second plurality of stages of multicast switches, read, once from storage separate from the circuit, each element of the packed input data as respective inputs of the circuit, route the packed input data through the circuit according to the packed control data, and store resultant packed data from the circuit into the packed data destination.

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