公开(公告)号：US20230209799A1

公开(公告)日：2023-06-29

申请号：US17560927

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Dan Lavric ,  Leonard Guler ,  YenTing Chiu ,  Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  Tahir Ghani

IPC: H01L27/11 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1108 ,  H01L29/4908 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/78696 ,  H01L29/6684 ,  H01L29/66742

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

公开(公告)号：US20250113598A1

公开(公告)日：2025-04-03

申请号：US18375314

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Dan Lavric ,  Jubin Nathawat ,  Orb Acton ,  Michal Mleczko ,  Owen Loh ,  Michael L. Hattendorf

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51

Abstract: An integrated circuit (IC) device includes n- and p-type transistors with and without threshold voltage shifts using a common dopant material in a gate dielectric. The IC device includes at least four threshold voltage for each of n- and p-type transistors. Besides volumeless doping of gate dielectrics, work function metals are used in both n- and p-type transistors. A single dipole dopant may be concurrently introduced into and through similar gate dielectrics in both n- and p-type transistors to achieve consistent threshold voltage shifts with minimal process variation.

公开(公告)号：US20240332290A1

公开(公告)日：2024-10-03

申请号：US18129700

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Shao-Ming Koh ,  Patrick Morrow ,  Nikhil Mehta ,  Leonard Guler ,  Sudipto Naskar ,  Alison Davis ,  Dan Lavric ,  Matthew Prince ,  Jeanne Luce ,  Charles Wallace ,  Cortnie Vogelsberg ,  Rajaram Pai ,  Caitlin Kilroy ,  Jojo Amonoo ,  Sean Pursel ,  Yulia Gotlib

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/32139 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.