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公开(公告)号：US10938404B1
公开(公告)日：2021-03-02
申请号：US16728163
申请日：2019-12-27
申请人： Intel Corporation
发明人： Ramon Sanchez , Kameran Azadet , Martin Clara , Daniel Gruber
摘要： A digital-to-analog converter is provided. The digital-to-analog converter comprises an input configured to receiving a first digital control code for controlling a plurality of digital-to-analog converter cells. Further, the digital-to-analog converter comprises a code converter circuit configured to converter the first digital control code to a second digital control code. Further, the digital-to-analog converter comprises a shift code generation circuit configured to generate a shift code based on a code difference between the first digital control code and a third digital control code. The digital-to-analog converter additionally comprises a bit-shifter circuit configured to bit-shift the second digital control code based on the shift code in order to obtain a modified second digital control code. The digital-to-analog converter comprises a cell activation circuit configured to selectively activate one or more of the plurality of digital-to-analog converter cells based on the modified second digital control code. Each activated digital-to-analog converter cell is configured to output a respective cell output signal. Further, the digital-to-analog converter comprises an output configured to output an analog output signal based on the cell output signals.
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公开(公告)号：US10651869B1
公开(公告)日：2020-05-12
申请号：US16364891
申请日：2019-03-26
发明人： Davide Ponton , Michael Kalcher , Alan Paussa , Edwin Thaller , Franz Kuttner , Daniel Gruber
摘要： A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.
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公开(公告)号：US11528182B2
公开(公告)日：2022-12-13
申请号：US17351288
申请日：2021-06-18
申请人： Intel Corporation
发明人： Kameran Azadet , Martin Clara , Daniel Gruber , Christian Lindholm , Hundo Shin
摘要： An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.
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公开(公告)号：US11038516B1
公开(公告)日：2021-06-15
申请号：US16886817
申请日：2020-05-29
申请人： Intel Corporation
发明人： Kameran Azadet , Ramon Sanchez , Albert Molina , Martin Clara , Daniel Gruber , Matteo Camponeschi
摘要： An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.
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公开(公告)号：US20210409065A1
公开(公告)日：2021-12-30
申请号：US16912741
申请日：2020-06-26
申请人： Intel Corporation
发明人： Daniel Gruber , L. Mark Elzinga , Martin Clara
摘要： The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.
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公开(公告)号：US11171663B2
公开(公告)日：2021-11-09
申请号：US16833729
申请日：2020-03-30
申请人： Intel Corporation
发明人： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
摘要： A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
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公开(公告)号：US10715185B1
公开(公告)日：2020-07-14
申请号：US16369317
申请日：2019-03-29
申请人： Intel Corporation
发明人： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
摘要： A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.
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公开(公告)号：US10608661B1
公开(公告)日：2020-03-31
申请号：US16369262
申请日：2019-03-29
申请人： Intel Corporation
发明人： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
摘要： A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
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公开(公告)号：US11637560B2
公开(公告)日：2023-04-25
申请号：US17455221
申请日：2021-11-17
申请人： Intel Corporation
发明人： Martin Clara , Daniel Gruber , Kameran Azadet
摘要： A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.
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10.发明授权公开(公告)号：US11378999B2
公开(公告)日：2022-07-05
申请号：US16724486
申请日：2019-12-23
申请人： Intel Corporation
发明人： Yu-Shan Wang , Martin Clara , Daniel Gruber , Hundo Shin , Kameran Azadet
摘要： An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.
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