公开(公告)号：US20160055922A1

公开(公告)日：2016-02-25

申请号：US14813010

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Joon-Sung Yang ,  Darshan Kobla ,  Liwei Ju ,  David Zimmerman

IPC: G11C29/00 ,  G11C29/04

CPC classification number: G11C29/70 ,  G11C29/025 ,  G11C29/04 ,  G11C29/4401 ,  G11C29/702 ,  G11C29/785 ,  G11C29/846 ,  G11C2213/71 ,  H01L22/22 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

公开(公告)号：US10224115B2

公开(公告)日：2019-03-05

申请号：US15589308

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Joon-Sung Yang ,  Darshan Kobla ,  Liwei Ju ,  David Zimmerman

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/04 ,  H01L21/66 ,  H01L25/065 ,  H01L23/48

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

公开(公告)号：US20190005176A1

公开(公告)日：2019-01-03

申请号：US15640448

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Rameshkumar Illikkal ,  Ananth Sankaranarayanan ,  David Zimmerman ,  Pratik M. Marolia ,  Suchit Subhaschandra ,  Dave Minturn

IPC: G06F17/50 ,  G06F21/76 ,  G06F17/30 ,  G06F3/06 ,  G06F9/445

Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.

公开(公告)号：US09646720B2

公开(公告)日：2017-05-09

申请号：US14813010

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Joon-Sung Yang ,  Darshan Kobla ,  Liwei Ju ,  David Zimmerman

IPC: G11C7/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/04 ,  H01L21/66 ,  H01L25/065 ,  H01L23/48

CPC classification number: G11C29/70 ,  G11C29/025 ,  G11C29/04 ,  G11C29/4401 ,  G11C29/702 ,  G11C29/785 ,  G11C29/846 ,  G11C2213/71 ,  H01L22/22 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

公开(公告)号：US11507430B2

公开(公告)日：2022-11-22

申请号：US16144962

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Rasika Subramanian ,  Francesc Guim Bernat ,  David Zimmerman

IPC: G06F9/50 ,  G06F11/34 ,  G06N3/04 ,  G06N3/08 ,  H04L41/5003 ,  H04L47/70

Abstract: Examples described herein can be used to determine and suggest a computing resource allocation for a workload request made from an edge gateway. The computing resource allocation can be suggested using computing resources provided by an edge server cluster. Telemetry data and performance indicators of the workload request can be tracked and used to determine the computing resource allocation. Artificial intelligence (AI) and machine learning (ML) techniques can be used in connection with a neural network to accelerate determinations of suggested computing resource allocations based on hundreds to thousands (or more) of telemetry data in order to suggest a computing resource allocation. Suggestions made can be accepted or rejected by a resource allocation manager for the edge gateway and the edge server cluster.

公开(公告)号：US11238203B2

公开(公告)日：2022-02-01

申请号：US15640448

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Rameshkumar Illikkal ,  Ananth Sankaranarayanan ,  David Zimmerman ,  Pratik M. Marolia ,  Suchit Subhaschandra ,  Dave Minturn

IPC: G06F30/331 ,  G06F21/76 ,  G06F3/06 ,  G06F9/445 ,  G06F12/0817 ,  G06F21/79 ,  G06F30/34

Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.