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公开(公告)号：US11114143B2
公开(公告)日：2021-09-07
申请号：US16283128
申请日：2019-02-22
Applicant: Intel Corporation
Inventor： Balaji Srinivasan , Sandeep K. Guliani , DerChang Kau , Ashir G. Shah
Abstract: A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.
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公开(公告)号：US12153823B2
公开(公告)日：2024-11-26
申请号：US17068369
申请日：2020-10-12
Applicant: Intel Corporation
Inventor： Davide Fugazza , Dany-Sebastien Ly-Gagnon , DerChang Kau
Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.
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公开(公告)号：US20220084589A1
公开(公告)日：2022-03-17
申请号：US16948300
申请日：2020-09-11
Applicant: Intel Corporation
Inventor： Balaji Srinivasan , Sandeep Kumar Guliani , Mase J. Taub , DerChang Kau , Ashir G. Shah
IPC: G11C13/00
Abstract: A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.
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公开(公告)号：US20220059166A1
公开(公告)日：2022-02-24
申请号：US16947886
申请日：2020-08-21
Applicant: Intel Corporation
Inventor： Balaji Srinivasan , Mase J. Taub , DerChang Kau
Abstract: A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.
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Patent Agency Ranking
公开(公告)号：US20220113892A1
公开(公告)日：2022-04-14
申请号：US17068369
申请日：2020-10-12
Applicant: Intel Corporation
Inventor： Davide Fugazza , Dany-Sebastien Ly-Gagnon , DerChang Kau
Abstract: A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.
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公开(公告)号：US09698344B2
公开(公告)日：2017-07-04
申请号：US15013517
申请日：2016-02-02
Applicant: INTEL CORPORATION
Inventor： DerChang Kau
CPC classification number: H01L45/06 , H01L27/2427 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/1293 , H01L45/141 , H01L45/16
Abstract: Embodiments of the present disclosure describe techniques and configurations for increasing thermal insulation in a resistance change memory device, also known as a phase change memory (PCM) device. In one embodiment, an apparatus includes a storage structure of a PCM device, the storage structure having a chalcogenide material, an electrode having an electrically conductive material, the electrode having a first surface that is directly coupled with the storage structure, and a dielectric film having a dielectric material, the dielectric film being directly coupled with a second surface of the electrode that is disposed opposite to the first surface. Other embodiments may be described and/or claimed.
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公开(公告)号：US11276465B1
公开(公告)日：2022-03-15
申请号：US16947886
申请日：2020-08-21
Applicant: Intel Corporation
Inventor： Balaji Srinivasan , Mase J. Taub , DerChang Kau
Abstract: A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.
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公开(公告)号：US10163982B2
公开(公告)日：2018-12-25
申请号：US15474154
申请日：2017-03-30
Applicant: Intel Corporation
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Fabio Pellizzer , Agostino Pirovano , DerChang Kau
IPC: H01L27/24 , H01L45/00 , H01L23/528 , G11C13/00
Abstract: Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages.
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9.发明申请公开(公告)号：US20160149127A1
公开(公告)日：2016-05-26
申请号：US15013517
申请日：2016-02-02
Applicant: INTEL CORPORATION
Inventor： DerChang Kau
IPC: H01L45/00
CPC classification number: H01L45/06 , H01L27/2427 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/1293 , H01L45/141 , H01L45/16
Abstract: Embodiments of the present disclosure describe techniques and configurations for increasing thermal insulation in a resistance change memory device, also known as a phase change memory (PCM) device. In one embodiment, an apparatus includes a storage structure of a PCM device, the storage structure having a chalcogenide material, an electrode having an electrically conductive material, the electrode having a first surface that is directly coupled with the storage structure, and a dielectric film having a dielectric material, the dielectric film being directly coupled with a second surface of the electrode that is disposed opposite to the first surface. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例描述了用于增加电阻变化存储器件（也称为相变存储器（PCM））器件中的热绝缘的技术和配置。 在一个实施例中，一种装置包括PCM装置的存储结构，所述存储结构具有硫族化物材料，具有导电材料的电极，所述电极具有与所述存储结构直接耦合的第一表面，以及电介质膜 具有电介质材料，所述电介质膜与所述电极的与所述第一表面相对设置的第二表面直接耦合。 可以描述和/或要求保护其他实施例。
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