公开(公告)号：US11543868B2

公开(公告)日：2023-01-03

申请号：US16898603

申请日：2020-06-11

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Robin A. Steinbrecher ,  Sandeep Ahuja ,  Michael Berktold ,  Timothy Y. Kam ,  Howard Chin ,  Phani Kumar Kandula ,  Krishnakanth V. Sistla

IPC: G06F1/20 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F3/041 ,  G06F11/30 ,  G06F1/32 ,  G06F1/26

Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.

公开(公告)号：US20160147291A1

公开(公告)日：2016-05-26

申请号：US14554384

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Ramamurthy Krithivas ,  Howard Chin ,  Ian M. Steiner ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多芯片封装（MCP）的第一芯片。 第一芯片包括至少一个核心和第一芯片温度控制（TC）逻辑，以响应于第一芯片的第一芯片温度超过第一阈值的指示来在MCP的第二芯片处断言第一功率调整信号。 处理器还包括导管，其包括将第一芯片耦合到MCP内的第二芯片的双向引脚。 导管将第一功率调整信号从第一芯片传输到第二芯片，第一功率调整信号将引起第二芯片的第二芯片功率消耗的调整。 描述和要求保护其他实施例。

公开(公告)号：US10048744B2

公开(公告)日：2018-08-14

申请号：US14554384

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Ramamurthy Krithivas ,  Howard Chin ,  Ian M. Steiner ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/20

Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

公开(公告)号：US20200301490A1

公开(公告)日：2020-09-24

申请号：US16898603

申请日：2020-06-11

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Robin A. Steinbrecher ,  Sandeep Ahuja ,  Michael Berktold ,  Timothy Y. Kam ,  Howard Chin ,  Phani Kumar Kandula ,  Krishnakanth V. Sistla

IPC: G06F1/20 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F3/041

Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.

公开(公告)号：US20180335831A1

公开(公告)日：2018-11-22

申请号：US16052375

申请日：2018-08-01

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Ramamurthy Krithivas ,  Howard Chin ,  Ian M. Steiner ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

公开(公告)号：US20160179158A1

公开(公告)日：2016-06-23

申请号：US14852859

申请日：2015-09-14

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Robin A. Steinbrecher ,  Sandeep Ahuja ,  Michael Berktold ,  Timothy Y. Kam ,  Howard Chin ,  Phani Kumar Kandula ,  Krishnakanth V. Sistla

IPC: G06F1/26 ,  G06F1/18 ,  G06F1/20 ,  G06F1/32

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F3/0412 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个核心和电源管理逻辑。 电源管理逻辑用于从包括处理器的封装内的多个管芯接收温度数据，并且确定多个温度控制裕度的最小温度控制裕度。 每个温度控制余量将基于与管芯相关联的相应的热控制温度并且还基于与管芯相关联的相应的温度数据来确定。 电源管理逻辑还可以生成包含最小温度控制余量的热报告，并存储热报告。 描述和要求保护其他实施例。