公开(公告)号：US20220109446A1

公开(公告)日：2022-04-07

申请号：US17555253

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Paul Rotker ,  Lai Guan Tang ,  Luis Hau ,  Ilya Ganusov

IPC: H03K19/0175

Abstract: An integrated circuit includes a region of logic circuits, first and second selector circuits, a first interface circuit for exchanging information with a first type of device according to a first communication protocol, and a second interface circuit for exchanging information with a second type of device according to a second communication protocol. The first selector circuit is configurable to provide signals between the region of the logic circuits and a selected one of the first or second interface circuits. The second selector circuit is configurable to provide signals between the selected one of the first or second interface circuits and the first or second type of device.

公开(公告)号：US11789641B2

公开(公告)日：2023-10-17

申请号：US17349592

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

公开(公告)号：US20220405005A1

公开(公告)日：2022-12-22

申请号：US17349592

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

IPC: G06F3/06

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

公开(公告)号：US20220187370A1

公开(公告)日：2022-06-16

申请号：US17687064

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Ilya Ganusov

IPC: G01R31/3185 ,  G01R31/317

Abstract: An integrated circuit includes first and second data storage circuits, first, second, and third shadow storage circuits, and first, second, and third multiplexer circuits. The first multiplexer circuit is configurable to provide a state of a data signal from the first data storage circuit to the first shadow storage circuit in a snapshot mode. The second multiplexer circuit is coupled between an output of the second data storage circuit and an input of the second shadow storage circuit. The third multiplexer circuit is coupled to the second multiplexer circuit. The third multiplexer circuit is configurable to provide a state of an output signal of the first shadow storage circuit to an input of the third shadow storage circuit in a scan mode bypassing the second shadow storage circuit.