公开(公告)号：US20250112153A1

公开(公告)日：2025-04-03

申请号：US18477838

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Inanc Meric ,  Keun Woo Park ,  Jeffrey Hicks

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L27/092

Abstract: Integrated circuit (IC) devices and systems with virtual ground nets, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with transistors, a first interconnect over the device layer, and a second interconnect under the device layer. Moreover, the first interconnect includes ground traces, which are electrically coupled to each other in the first interconnect or the second interconnect.

公开(公告)号：US11515251B2

公开(公告)日：2022-11-29

申请号：US15943009

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent Dorgan ,  Jeffrey Hicks ,  Inanc Meric

IPC: H01L23/525 ,  H01L29/78 ,  H01L23/64 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/105 ,  G11C11/40 ,  H01L27/112 ,  G11C17/16

Abstract: Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US12009433B2

公开(公告)日：2024-06-11

申请号：US16001837

申请日：2018-06-06

Applicant: Intel Corporation

Inventor： Van H. Le ,  Inanc Meric ,  Gilbert Dewey ,  Sean Ma ,  Abhishek A. Sharma ,  Miriam Reshotko ,  Shriram Shivaraman ,  Kent Millard ,  Matthew V. Metz ,  Wilhelm Melitz ,  Benjamin Chu-Kung ,  Jack Kavalieros

IPC: H01L29/786 ,  H01L21/28 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78678 ,  H01L21/28194 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/7869

Abstract: Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.

公开(公告)号：US11387366B2

公开(公告)日：2022-07-12

申请号：US16634517

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey ,  Shriram Shivaraman ,  Inanc Meric ,  Benjamin Chu-Kung

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/24 ,  H01L29/51 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US11348651B2

公开(公告)日：2022-05-31

申请号：US16147119

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Sarvesh Kulkarni ,  Vincent Dorgan ,  Inanc Meric ,  Venkata Krishna Rao Vangara ,  Uddalak Bhattacharya ,  Jeffrey Hicks

IPC: G11C17/16 ,  G11C17/18

Abstract: Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded. The word line and the source line are configured to cause hot carrier injection into the second transistor when the first supply voltage is applied to the word line and the source line, and the first bit line is floated and the second bit line is grounded. Methods utilizing this technology for generating a multi-time programmable non-volatile memory and a random number generator for physical unclonable function applications are included in this disclosure.