公开(公告)号：US11348651B2

公开(公告)日：2022-05-31

申请号：US16147119

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Sarvesh Kulkarni ,  Vincent Dorgan ,  Inanc Meric ,  Venkata Krishna Rao Vangara ,  Uddalak Bhattacharya ,  Jeffrey Hicks

IPC: G11C17/16 ,  G11C17/18

Abstract: Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded. The word line and the source line are configured to cause hot carrier injection into the second transistor when the first supply voltage is applied to the word line and the source line, and the first bit line is floated and the second bit line is grounded. Methods utilizing this technology for generating a multi-time programmable non-volatile memory and a random number generator for physical unclonable function applications are included in this disclosure.

公开(公告)号：US20220415807A1

公开(公告)日：2022-12-29

申请号：US17358971

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Chytra Pawashe ,  Lei Jiang ,  Colin Landon ,  Daniel Pantuso ,  Edwin Ramayya ,  Jeffrey Hicks ,  Mehmet Koker Aykol

IPC: H01L23/538 ,  H01L23/36

Abstract: A device structure includes a first interconnect layer, a second interconnect layer, a device layer including a comprising a plurality of devices, where the device layer is between the first interconnect layer and the second interconnect layer. The device structure further includes a dielectric layer adjacent the second interconnect layer, where the dielectric layer includes one or more of metallic dopants or a plurality of metal structures, wherein the plurality of metal structures is electrically isolated from interconnect structures but in contact with a dielectric material of the second interconnect layer, and where the individual ones of the plurality of metal structures is above a region including at least some of the plurality of devices. The device structure further includes a substrate adjacent to the dielectric layer and a heat sink coupled with the substrate.

公开(公告)号：US11515251B2

公开(公告)日：2022-11-29

申请号：US15943009

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent Dorgan ,  Jeffrey Hicks ,  Inanc Meric

IPC: H01L23/525 ,  H01L29/78 ,  H01L23/64 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/105 ,  G11C11/40 ,  H01L27/112 ,  G11C17/16

Abstract: Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US11239149B2

公开(公告)日：2022-02-01

申请号：US15942952

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent Dorgan ,  Jeffrey Hicks ,  Uddalak Bhattacharya ,  Zhanping Chen ,  Walid Hafez

IPC: G11C11/00 ,  H01L23/50 ,  H01L21/768 ,  H01L21/77

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.

公开(公告)号：US20250112153A1

公开(公告)日：2025-04-03

申请号：US18477838

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Inanc Meric ,  Keun Woo Park ,  Jeffrey Hicks

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L27/092

Abstract: Integrated circuit (IC) devices and systems with virtual ground nets, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with transistors, a first interconnect over the device layer, and a second interconnect under the device layer. Moreover, the first interconnect includes ground traces, which are electrically coupled to each other in the first interconnect or the second interconnect.

公开(公告)号：US20240370615A1

公开(公告)日：2024-11-07

申请号：US18345972

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Lei Jiang ,  Daniel Pantuso ,  Satish Sethuraman ,  Kambiz Komeyli ,  Jeffrey Hicks

IPC: G06F30/327

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed An apparatus comprising: programmable circuitry; interface circuitry; and instructions to program the programmable circuitry to: map one or more circuit layouts to a hardware description language model of a circuit to generate a power density map for the circuit; estimate a temperature gradient between a first area of the circuit and a second area of the circuit based on the power density map; identify the first area as a hotspot based on the temperature gradient exceeding a threshold value; and compensate for a predicted timing change due to the temperature gradient.

公开(公告)号：US11264317B2

公开(公告)日：2022-03-01

申请号：US15942999

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent Dorgan ,  Jeffrey Hicks ,  Miriam Reshotko ,  Abhishek Sharma ,  Ilan Tsameret

IPC: H01L23/50 ,  H01L23/48 ,  H01L29/51 ,  G11C17/16 ,  H01L21/82 ,  H01L23/522 ,  H01L23/525 ,  H01L23/498

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.