公开(公告)号：US11237990B2

公开(公告)日：2022-02-01

申请号：US16901517

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Alexander Slota ,  James Coleman ,  Rajkumar Khandelwal ,  Anil Kumar

IPC: G06F13/28 ,  G06F13/12 ,  G06F12/1081

Abstract: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

公开(公告)号：US10684963B2

公开(公告)日：2020-06-16

申请号：US16236057

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Alexander Slota ,  James Coleman ,  Rajkumar Khandelwal ,  Anil Kumar

IPC: G06F13/28 ,  G06F13/12 ,  G06F12/1081

Abstract: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

公开(公告)号：US12301697B2

公开(公告)日：2025-05-13

申请号：US17132058

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vikram Dadwal ,  James Coleman ,  Alexander Slota

IPC: G06F1/12 ,  G06F1/14 ,  H04L7/04

Abstract: Systems and techniques for an heterogeneous clock management solution for industrial systems are described herein. In an example, a system includes a clock management circuit adapted to receive core timing information from a core of an integrated circuit. The clock management circuit is further adapted to correlate the core timing information with a reference clock. The clock management circuit is further adapted to output frequency and time offset of the reference clock to the core timing information. The system includes an execution circuit adapted to schedule a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset. The execution circuit is further adapted to issue a command to execute the transaction at the scheduled time.

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

公开(公告)号：US11991054B2

公开(公告)日：2024-05-21

申请号：US17063991

申请日：2020-10-06

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned M. Smith ,  Sunil Cheruvu ,  Alexander Bachmutsky ,  James Coleman

IPC: H04L12/24 ,  H04L12/26 ,  H04L29/08 ,  H04L41/50 ,  H04L41/5003 ,  H04L41/5022 ,  H04L43/087 ,  H04L67/288

CPC classification number: H04L41/5022 ,  H04L41/5003 ,  H04L41/5096 ,  H04L43/087 ,  H04L67/288

Abstract: Methods and apparatus for jitter-less distributed Function as a Service (FaaS) using flavor clustering. A set of FaaS functions clustered by flavor chaining is implemented to deploy one or more FaaS flavor clusters on one or more edge nodes, wherein each flavor is defined by a set of resource requirements mapped into a jitter Quality of Service (QoS) and is executed on at least one hardware computing component on the one or more edge nodes. One or more jitter controllers are implemented to control and monitor execution of FaaS functions in the one or more FaaS flavor clusters such that the functions are executed to meet jitter-less QoS requirements. Jitter controllers include platform jitter-less function controllers in edge nodes and a data center FaaS jitter-less controller. A jitter-less Software Defined Wide Area Network (SD-WAN) network controller is also provided to provide network resources used by FaaS flavor clusters and satisfy connectivity requirements between the edge nodes.

公开(公告)号：US20210064554A1

公开(公告)日：2021-03-04

申请号：US16901517

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Alexander Slota ,  James Coleman ,  Rajkumar Khandelwal ,  Anil Kumar

IPC: G06F13/12 ,  G06F12/1081 ,  G06F13/28

Abstract: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.