公开(公告)号：US12079153B2

公开(公告)日：2024-09-03

申请号：US18199042

申请日：2023-05-18

Applicant: Intel Corporation

Inventor： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley Burres ,  Pawel Szymanski ,  Yi-Feng Liu

IPC: G06F13/40 ,  G06F9/4401 ,  G06F9/445

CPC classification number: G06F13/4027 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/44505 ,  G06F13/4022

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

公开(公告)号：US10956351B2

公开(公告)日：2021-03-23

申请号：US16566576

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley Burres ,  Pawel Szymanski ,  Yi-Feng Liu

IPC: G06F13/364 ,  G06F13/40 ,  G06F9/4401 ,  G06F9/445

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

公开(公告)号：US11693807B2

公开(公告)日：2023-07-04

申请号：US17207135

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley A. Burres ,  Pawel Szymanski ,  Yi-Feng Liu

IPC: G06F13/40 ,  G06F9/4401 ,  G06F9/445

CPC classification number: G06F13/4027 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/44505 ,  G06F13/4022

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

公开(公告)号：US20190205042A1

公开(公告)日：2019-07-04

申请号：US15856780

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Phani Kumar Kandula ,  Bharat S. Pillilli ,  Suresh Chemudupati ,  Yi-Feng Liu

IPC: G06F3/06 ,  G06F9/4401

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0685 ,  G06F9/4403

Abstract: An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.