公开(公告)号：US12248561B2

公开(公告)日：2025-03-11

申请号：US17485421

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Ravi Sahita ,  Utkarsh Y KAKAIYA ,  Abhishek Basak ,  Lee Albion ,  Filip Schmole ,  Rupin Vakharwala ,  Vinit M Abraham ,  Raghunandan Makaram

IPC: G06F21/54 ,  G06F9/455 ,  G06F13/40 ,  G06F21/56

Abstract: Apparatus and method for role-based register protection. For example, one embodiment of an apparatus comprises: one or more processor cores to execute instructions and process data, the one or more processor cores to execute one or more security instructions to protect a virtual machine or trusted application from a virtual machine monitor (VMM) or operating system (OS); an interconnect fabric to couple the one or more processor cores to a device; and security hardware logic to determine whether to allow a read or write transaction directed to a protected register to proceed over the interconnect fabric, the security hardware logic to evaluate one or more security attributes associated with an initiator of the transaction to make the determination.

公开(公告)号：US11762802B2

公开(公告)日：2023-09-19

申请号：US16914339

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Debendra Das Sharma ,  Lee Albion

IPC: G06F13/42 ,  G06F1/10

CPC classification number: G06F13/42 ,  G06F1/10 ,  G06F13/4221 ,  G06F2213/0026

Abstract: An interface for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header of a packet based on the interconnect protocol and second lanes to carry metadata for the header. The interface additionally includes a data channel implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet and fourth lanes to carry metadata for the payload.

公开(公告)号：US20250103397A1

公开(公告)日：2025-03-27

申请号：US18401399

申请日：2023-12-30

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Daniel Joe ,  Filip Schmole ,  Philip Abraham ,  Stephen R. Van Doren ,  Priya Autee ,  Rajesh M. Sankaran ,  Anthony Luck ,  Philip Lantz ,  Eric Wehage ,  Edwin Verplanke ,  James Coleman ,  Scott Oehrlein ,  David M. Lee ,  Lee Albion ,  David Harriman ,  Vinit Mathew Abraham ,  Yi-Feng Liu ,  Manjula Peddireddy ,  Robert G. Blankenship

IPC: G06F9/50

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.