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    INTERFERENCE TESTING
    2.
    发明申请
    INTERFERENCE TESTING 有权
    干扰测试

    公开(公告)号：US20150280781A1

    公开(公告)日：2015-10-01

    申请号：US14229460

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Alexey Kostinsky ,  Tomer Levy ,  Paul S. Cheses ,  Danny Naiger ,  Theodore Z. Schoenborn ,  Christopher P. Mozak ,  Nagi Aboulenien ,  James M. Shehadi

    IPC: H04B3/46

    CPC classification number: H04B3/487 ,  G01R31/28 ,  G01R31/31855 ,  G06F11/00

    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

    Abstract translation: 在一个示例中，控制器包括至少部分地包括硬件逻辑的逻辑，其被配置为通过在第一组伪随机模式上产生第一组伪随机模式来实现在包括受害者通道和第一侵入者通道的通信互连上的干扰测试的第一次迭代 受害者车道和侵略者车道，并通过在第一侵略者车道上推进种子来实施干扰测试的第二次迭代。 可以描述其他示例。

    Transaction-level testing of memory I/O and memory device
    4.
    发明授权
    Transaction-level testing of memory I/O and memory device 有权
    内存I / O和内存设备的事务级别测试

    公开(公告)号：US08996934B2

    公开(公告)日：2015-03-31

    申请号：US13631961

    申请日：2012-09-29

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Theodore Z. Schoenborn ,  James M. Shehadi

    IPC: G11C29/00 ,  G11C29/08 ,  G11C29/56

    CPC classification number: G11C29/08 ,  G11C29/56 ,  G11C2029/5602

    Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.

    Abstract translation: 存储器子系统包括耦合到存储器控制器的测试引擎，其可以绕过存储器地址解码器来向存储器控制器提供存储器访问事务。 测试引擎接收到一个命令，使其生成事务以实现内存测试。 该命令标识要实现的测试，并且测试引擎生成一个或多个存储器访问事务以在存储器设备上实现测试。 测试引擎将事务传递到内存控制器，可以使用其调度程序来调度命令。 因此，交易在存储设备中引起确定性行为，因为交易按照提供的方式执行，同时测试设备的实际操作。

    Memory subsystem data bus stress testing
    6.
    发明授权
    Memory subsystem data bus stress testing 有权
    内存子系统数据总线压力测试

    公开(公告)号：US09009531B2

    公开(公告)日：2015-04-14

    申请号：US13706177

    申请日：2012-12-05

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Theodore Z. Schoenborn ,  James M. Shehadi ,  David G. Ellis

    IPC: G06F11/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/36 ,  G11C29/50 ,  G11C29/52

    CPC classification number: G11C29/02 ,  G11C29/022 ,  G11C29/06 ,  G11C29/36 ,  G11C29/50012 ,  G11C29/52

    Abstract: A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.

    Abstract translation: 存储器子系统包括存储器控制器的测试信号发生器，其响应于存储器控制器接收测试事务而产生测试数据信号。 测试事务指示在相关联的存储设备上执行的一个或多个I / O操作。 测试信号发生器可以从各种不同的模式发生器产生数据信号。 存储器控制器调度器调度测试数据信号模式，并将其发送到存储器件。 然后，存储器件可以执行I / O操作来实现测试事务。 存储器控制器可以读取写入存储器件的特定地址的数据，并将回读数据与预期数据进行比较。 当回读数据和预期数据不匹配时，存储器控制器可以记录错误。 该错误可以包括错误的具体地址，特定数据和/或编码数据。

    Functional memory array testing with a transaction-level test engine
    7.
    发明授权
    Functional memory array testing with a transaction-level test engine 有权
    功能性内存阵列测试与事务级测试引擎

    公开(公告)号：US09003246B2

    公开(公告)日：2015-04-07

    申请号：US13631962

    申请日：2012-09-29

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Theodore Z. Schoenborn ,  James M. Shehadi

    IPC: G11C29/00 ,  G11C29/08 ,  G11C29/56

    CPC classification number: G11C29/08 ,  G11C29/56 ,  G11C2029/5602

    Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.

    Abstract translation: 存储器子系统包括耦合到存储器控制器的测试引擎，其可以绕过存储器地址解码器来向存储器控制器提供存储器访问事务。 测试引擎硬件可配置为不同的测试。 测试引擎识别响应于接收到指示要执行的测试的软件指令来迭代测试序列的地址范围。 对于测试的每次迭代，测试引擎通过选定的硬件生成内存访问事务，从范围中选择一个地址，并将事务发送到内存控制器。 存储器控制器响应于事务来调度存储器设备命令，这导致存储器件执行操作来执行事务。

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