公开(公告)号：US09983880B2

公开(公告)日：2018-05-29

申请号：US14497974

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Rekai Gonzalez-Alberquilla ,  Tanausu Ramirez ,  Josep M. Codina ,  Enric Gibert Codina

IPC: G06F9/38 ,  G06F9/48 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036

CPC classification number: G06F9/3851 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3867 ,  G06F9/4881 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/68 ,  G06F2212/684

Abstract: An apparatus and method are described for improved thread selection. For example, one embodiment of a processor comprises: first logic to maintain a history table comprising a plurality of entries, each entry in the table associated with an instruction and including history data indicating prior hits and/or misses to a cache level and/or a translation lookaside buffer (TLB) for that instruction; and second logic to select a particular thread for execution at a particular processor pipeline stage based on the history data.

公开(公告)号：US10157063B2

公开(公告)日：2018-12-18

申请号：US13631402

申请日：2012-09-28

Applicant: INTEL CORPORATION

Inventor： Polychronis Xekalakis ,  Pedro Marcuello ,  Alejandro Vicente Martinez ,  Christos E. Kotselidis ,  Grigorios Magklis ,  Fernando Latorre ,  Raul Martinez ,  Josep M. Codina ,  Enric Gibert Codina ,  Crispin Gomez Requena ,  Antonio Gonzelez ,  Mirem Hyuseinova ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

公开(公告)号：US20190004916A1

公开(公告)日：2019-01-03

申请号：US16026870

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Raul Martinez ,  Enric Gibert Codina ,  Pedro Lopez ,  Marti Torrents Lapuerta ,  Polychronis Xekalakis ,  Georgios Tournavitis ,  Kyriakos A. Stavrou ,  Demos Pavlou ,  Daniel Ortega ,  Alejandro Martinez Vicente ,  Pedro Marcuello ,  Grigorios Magklis ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos Kotselidis ,  Fernando Latorre ,  Marc Lupon ,  Carlos Madriles

IPC: G06F11/30 ,  G06F12/0862 ,  G06F11/34

Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.