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公开(公告)号:US12243611B2
公开(公告)日:2025-03-04
申请号:US17856897
申请日:2022-07-01
Applicant: Intel Corporation
Inventor: Minki Cho , Daniel Nemiroff , Carlos Tokunaga , James W. Tschanz , Kah Meng Yeem , Yaxin Shui
IPC: G11C5/00
Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.
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公开(公告)号:US09891282B2
公开(公告)日:2018-02-13
申请号:US14998200
申请日:2015-12-24
Applicant: Intel Corporation
Inventor: Lakshminarayana Pappu , Robert P. Adler , Suketu U. Bhatt , Robert De Gruijl , Kah Meng Yeem
IPC: G01R31/28 , G01R31/3177 , H03K19/177 , H03K19/21
CPC classification number: G01R31/3177 , H03K19/17704 , H03K19/21
Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.
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公开(公告)号:US20240005962A1
公开(公告)日:2024-01-04
申请号:US17856897
申请日:2022-07-01
Applicant: Intel Corporation
Inventor: Minki Cho , Daniel Nemiroff , Carlos Tokunaga , James W. Tschanz , Kah Meng Yeem , Yaxin Shui
IPC: G11C5/00
CPC classification number: G11C5/005
Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.
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公开(公告)号:US20170184666A1
公开(公告)日:2017-06-29
申请号:US14998200
申请日:2015-12-24
Applicant: Intel Corporation
Inventor: Lakshminarayana Pappu , Robert P. Adler , Suketu U. Bhatt , Robert De Gruijl , Kah Meng Yeem
IPC: G01R31/3177 , H03K19/21 , H03K19/177
CPC classification number: G01R31/3177 , H03K19/17704 , H03K19/21
Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.
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