公开(公告)号：US20220271855A1

公开(公告)日：2022-08-25

申请号：US17668265

申请日：2022-02-09

Applicant: Intel Corporation

Inventor： Daniel Christian BIEDERMAN ,  Pat WANG ,  Mark BORDOGNA ,  Raghuram NARAYAN ,  Renuka SAPKAL

IPC: H04J3/06 ,  H04J14/08

Abstract: Optical and electrical modules with enhanced features and associated apparatus and methods. The optical modules are configured to implement one or more features that are offloaded from Ethernet devices to which the optical modules are configured to be attached. The features include support for timestamping packets and preamble using IEEE 1588 Precision Time Protocol (PTP) profiles, support for implementing IEEE 1588 one-step operations, support for implementing IEEE 1588 Ethernet Synchronous Clocks (SyncE) profiles, support for In-Band Network Telemetry (INT), and support for implementing a MACsec security protocol defined by IEEE standard 802.1AD. The enhanced features provided by the optical modules enable Ethernet devices to be upgraded to support the enhanced features by replacing conventional optical modules with the optical modules disclosed herein. Support for White Rabbit IEEE PTP and SyncE profiles is also provided.

公开(公告)号：US20250088342A1

公开(公告)日：2025-03-13

申请号：US18960953

申请日：2024-11-26

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Jonathan A. ROBINSON ,  Srinivasan S. IYENGAR

IPC: H04L7/00

Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a device main timer and (ii) a relationship between a network timer source and the network interface device main timer.

公开(公告)号：US20240204899A1

公开(公告)日：2024-06-20

申请号：US18426209

申请日：2024-01-29

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Zoltan FODOR

IPC: H04J3/06

CPC classification number: H04J3/0667 ,  H04J3/0682

Abstract: Examples described herein relate to a first network interface controller comprising a first network interface, first timer, and a first signal transceiver and circuitry to reduce offset between the first timer of the first network interface controller and a second timer of a second network interface controller. The circuitry to reduce offset between the first timer of the first network interface controller and a second timer of a second network interface controller based on a first signal transmitted over a communication line from the first signal transceiver to the second network interface controller and also based on the first signal transmitted from the second network interface controller back to the first network interface controller over the communication line.

公开(公告)号：US20230370241A1

公开(公告)日：2023-11-16

申请号：US18206027

申请日：2023-06-05

Applicant: Intel Corporation

Inventor： Daniel Christian BIEDERMAN ,  Mark BORDOGNA ,  Christopher S. HALL ,  James COLEMAN

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  H04L7/0087

Abstract: Examples described herein relate to a in a group of servers: the servers attempting to perform timing synchronization based on a first group of timing signals sent via a first path. In some examples, the first comprises a first connection and based on disruption of communications by the first connection between servers in the group of servers. In some examples, the servers attempting to perform timing synchronization based on a second group of timing signals sent via a second path. In some examples, the second path does not traverse the first connection.

公开(公告)号：US20230367362A1

公开(公告)日：2023-11-16

申请号：US18198150

申请日：2023-05-16

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Jonathan A. ROBINSON

IPC: G06F1/14 ,  H04L43/106 ,  G06F9/54 ,  G06F1/12

CPC classification number: G06F1/14 ,  H04L43/106 ,  G06F9/542 ,  G06F1/12

Abstract: Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.

公开(公告)号：US20230077631A1

公开(公告)日：2023-03-16

申请号：US17992747

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Daniel Christian BIEDERMAN ,  Mark BORDOGNA

IPC: H04L43/087 ,  H04L41/5009 ,  G06F1/12

Abstract: Examples described herein relate to a network interface device that includes a host interface; a network interface; and circuitry to: receive time information of a device that executes a service and based on the time information being outside of a permitted jitter range for the service, perform one or more actions to cause execution of the service on a device that operates based on a clock signal within a permitted jitter range.

公开(公告)号：US20210211214A1

公开(公告)日：2021-07-08

申请号：US17205869

申请日：2021-03-18

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Srinivasan S. IYENGAR

IPC: H04J3/06 ,  H04L12/26 ,  H04L29/06

Abstract: Methods and apparatus for data plane control of network time sync protocol in multi-host systems. A network interface controller (NIC) is configured to implement a network data plane that is associated with a software-based control plane implemented in the multi-host system. The NIC includes a primary timer and secondary timers at distributed endpoints such as network ports. The NIC receives network time packets having network timestamps and employs a secondary timer to associate a local timestamp with the packets. The network and local timestamps are compared by a network intellectual property block (network IP) in the data plane datapath to adjust the primary and secondary timer(s) to match the network time. The network IP uses a 2-bit wire protocol to increment and/or decrement the primary and secondary timer(s) that enables the timers to be adjusted with a nanosecond granularity.

公开(公告)号：US20250125896A1

公开(公告)日：2025-04-17

申请号：US19000227

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： David R. MULVIHILL ,  Srinivasan S. IYENGAR ,  Mark BORDOGNA ,  Subrahmanya Kumar KUCHIBHOTLA

IPC: H04J3/06 ,  H04W56/00

Abstract: Examples described herein relate to a timing source. In some examples, the timing source generates a clock signal by synchronization with a second clock signal from a crystal source and subsequent synchronization with a third clock signal. In some examples, the third clock signal is synchronized to timing signals received in Ethernet packets. In some examples, the crystal source is to provide the second clock signal to the circuitry via the interface.

公开(公告)号：US20220337683A1

公开(公告)日：2022-10-20

申请号：US17500576

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Daniel Christian BIEDERMAN ,  Mark BORDOGNA ,  Srinivasan S. IYENGAR

IPC: H04L29/06

Abstract: Examples described herein relate to a network interface device that includes circuitry to determine a target time domain in which to translate a time stamp associated with a workload and identify the target time domain to cause translation of the time stamp associated with the workload to the target time domain. In some examples, the network interface device stores time domain translation parameters of time stamps from a first time domain to one or more time domains and the network interface device translates the time stamp from the first time domain to the one or more time domains. In some examples, the network interface device comprises circuitry to store time domain translation parameters of time stamps from a first time domain to one or more time domains and the server is to perform translation of the time stamp from the first time domain to the one or more time domains based on the time domain translation parameters.

公开(公告)号：US20220006607A1

公开(公告)日：2022-01-06

申请号：US17475200

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Mark BORDOGNA ,  Jonathan A. ROBINSON ,  Srinivasan S. IYENGAR

IPC: H04L7/00

Abstract: Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.