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1.发明公开公开(公告)号：US20230377267A1
公开(公告)日：2023-11-23
申请号：US17852216
申请日：2022-06-28
Applicant: Intel Corporation
Inventor： Lorenzo TESSARI , Addis DITTEBRANDT , Michael DOYLE , Carsten BENTHIN
CPC classification number: G06T17/20 , G06T15/005 , G06T15/06 , G06T1/20
Abstract: A method and apparatus for efficiently constructing a bounding volume hierarchy (BVH). For example, one embodiment of an apparatus comprises: a primitive sampler to identify a representative subset of input primitives of a graphics scene; bounding volume hierarchy (BVH) builder hardware logic to construct an approximate BVH based on the representative subset of input primitives; hardware logic to insert input primitives not in the representative subset into leaves of the approximate BVH; and the BVH builder or a different BVH builder to construct a final BVH based on the primitives inserted into the leaves of the approximate BVH.
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公开(公告)号：US20230377247A1
公开(公告)日：2023-11-23
申请号：US18306821
申请日：2023-04-25
Applicant: Intel Corporation
Inventor： Michael DOYLE , Karthik VAIDYANATHAN
CPC classification number: G06T15/10 , G06T1/60 , G06T9/00 , G06T15/06 , G06T2210/12
Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.
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公开(公告)号：US20230350641A1
公开(公告)日：2023-11-02
申请号：US17699063
申请日：2022-03-18
Applicant: INTEL CORPORATION
Inventor： Lorenzo TESSARI , Michael DOYLE
IPC: G06F7/58
CPC classification number: G06F7/582
Abstract: Apparatus and method for generating a quasi-random sequence. For example, one embodiment of an apparatus comprises: a graphics processor comprising execution resources to execute graphics instructions; and quasi-random sequence generation logic implemented, at least in part, in program code executed by an execution unit, the quasi-random sequence generation logic to generate a Sobol number sequence to be used by the graphics processor for rendering operations, the Sobol sequence generator to perform the operations of: generating white noise bits; mixing the white noise bits with Sobol bits to generate a quasi-random result sequence.
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公开(公告)号：US20230298254A1
公开(公告)日：2023-09-21
申请号：US17699060
申请日：2022-03-18
Applicant: INTEL CORPORATION
Inventor： Carsten BENTHIN , Radoslaw J. DRABINSKI , Michael DOYLE , Josh BARCZAK
CPC classification number: G06T15/06 , G06T15/08 , G06T17/10 , G06T2210/12
Abstract: Apparatus and method for accelerating bounding box merge operations. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to be used to determine ray traversal results when traversing a ray through a bounding volume hierarchy (BVH), the BVH comprising a plurality of axis-aligned bounding boxes (AABBs); and a bounding box (BB) merge accelerator coupled to one or more execution units and coupled to a local memory in which to store a group of the AABBs, the BB merge accelerator, in response to the one or more EUs, to determine a second AABB to merge with a first AABB in accordance with a specified distance function.
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公开(公告)号：US20210049808A1
公开(公告)日：2021-02-18
申请号：US17003011
申请日：2020-08-26
Applicant: INTEL CORPORATION
Inventor： Scott JANUS , Prasoonkumar SURTI , Karthik VAIDYANATHAN , Alexey SUPIKOV , Gabor LIKTOR , Carsten BENTHIN , Philip LAWS , Michael DOYLE
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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Patent Agency Ranking
公开(公告)号：US20240233244A1
公开(公告)日：2024-07-11
申请号：US18413286
申请日：2024-01-16
Applicant: INTEL CORPORATION
Inventor： Scott JANUS , Prasoonkumar SURTI , Karthik VAIDYANATHAN , Alexey SUPIKOV , Gabor LIKTOR , Carsten BENTHIN , Philip LAWS , Michael DOYLE
CPC classification number: G06T15/06 , G06T1/60 , G06T15/005 , G06T17/005 , G06T2210/21
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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7.发明公开公开(公告)号：US20240013470A1
公开(公告)日：2024-01-11
申请号：US18371614
申请日：2023-09-22
Applicant: Intel Corporation
Inventor： Gabor LIKTOR , Karthik VAIDYANATHAN , Jefferson AMSTUTZ , Atsuo KUWAHARA , Michael DOYLE , Travis SCHLUESSLER
CPC classification number: G06T15/005 , G06T1/60 , G06T15/06 , G06T2210/21
Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
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8.发明申请公开(公告)号：US20220414970A1
公开(公告)日：2022-12-29
申请号：US17868618
申请日：2022-07-19
Applicant: Intel Corporation
Inventor： Gabor LIKTOR , Karthik VAIDYANATHAN , Jefferson AMSTUTZ , Atsuo KUWAHARA , Michael DOYLE , Travis SCHLUESSLER
Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
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公开(公告)号：US20220327763A1
公开(公告)日：2022-10-13
申请号：US17723772
申请日：2022-04-19
Applicant: INTEL CORPORATION
Inventor： Scott JANUS , Prasoonkumar SURTI , Karthik VAIDYANATHAN , Alexey SUPIKOV , Gabor LIKTOR , Carsten BENTHIN , Philip LAWS , Michael DOYLE
Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.
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10.发明公开公开(公告)号：US20240046403A1
公开(公告)日：2024-02-08
申请号：US18231379
申请日：2023-08-08
Applicant: Intel Corporation
Inventor： Michael DOYLE , Travis SCHLUESSLER , Gabor LIKTOR , Atsuo KUWAHARA , Jefferson AMSTUTZ
IPC: G06T1/20 , G06F16/901 , G06F9/38 , G06F9/50 , G06T15/00
CPC classification number: G06T1/20 , G06F16/9027 , G06F9/3877 , G06F9/3891 , G06F9/5077 , G06T15/005 , G06T15/06
Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.
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