公开(公告)号：US20220262063A1

公开(公告)日：2022-08-18

申请号：US17677109

申请日：2022-02-22

申请人： INTEL CORPORATION

发明人： Karol SZERSZEN ,  Prasoonkumar SURTI ,  Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Sven WOOP

IPC分类号： G06T15/06 ,  G06T15/08 ,  G06T1/20 ,  G06T17/10 ,  G06T15/00

摘要： Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US20240104825A1

公开(公告)日：2024-03-28

申请号：US18376098

申请日：2023-10-03

申请人： INTEL CORPORATION

发明人： Karol SZERSZEN ,  Prasoonkumar SURTI ,  Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Sven WOOP

IPC分类号： G06T15/06 ,  G06T1/20 ,  G06T15/00 ,  G06T15/08 ,  G06T17/10

CPC分类号： G06T15/06 ,  G06T1/20 ,  G06T15/005 ,  G06T15/08 ,  G06T17/10

摘要： Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US20210350609A1

公开(公告)日：2021-11-11

申请号：US17223395

申请日：2021-04-06

申请人： Intel Corporation

发明人： Ingo WALD ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Carson BROWNLEE ,  Johannes GUENTHER ,  Jefferson D. AMSTUTZ

IPC分类号： G06T15/06 ,  G06T15/00

摘要： An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.

公开(公告)号：US20210049808A1

公开(公告)日：2021-02-18

申请号：US17003011

申请日：2020-08-26

申请人： INTEL CORPORATION

发明人： Scott JANUS ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Alexey SUPIKOV ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Philip LAWS ,  Michael DOYLE

IPC分类号： G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

摘要： Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20240233244A1

公开(公告)日：2024-07-11

申请号：US18413286

申请日：2024-01-16

申请人： INTEL CORPORATION

发明人： Scott JANUS ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Alexey SUPIKOV ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Philip LAWS ,  Michael DOYLE

IPC分类号： G06T15/06 ,  G06T1/60 ,  G06T15/00 ,  G06T17/00

CPC分类号： G06T15/06 ,  G06T1/60 ,  G06T15/005 ,  G06T17/005 ,  G06T2210/21

摘要： Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20240013470A1

公开(公告)日：2024-01-11

申请号：US18371614

申请日：2023-09-22

申请人： Intel Corporation

发明人： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC分类号： G06T15/00 ,  G06T1/60 ,  G06T15/06

CPC分类号： G06T15/005 ,  G06T1/60 ,  G06T15/06 ,  G06T2210/21

摘要： Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20220414970A1

公开(公告)日：2022-12-29

申请号：US17868618

申请日：2022-07-19

申请人： Intel Corporation

发明人： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC分类号： G06T15/00 ,  G06T1/60 ,  G06T15/06

摘要： Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20220327763A1

公开(公告)日：2022-10-13

申请号：US17723772

申请日：2022-04-19

申请人： INTEL CORPORATION

发明人： Scott JANUS ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Alexey SUPIKOV ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Philip LAWS ,  Michael DOYLE

IPC分类号： G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

摘要： Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20240046403A1

公开(公告)日：2024-02-08

申请号：US18231379

申请日：2023-08-08

申请人： Intel Corporation

发明人： Michael DOYLE ,  Travis SCHLUESSLER ,  Gabor LIKTOR ,  Atsuo KUWAHARA ,  Jefferson AMSTUTZ

IPC分类号： G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00

CPC分类号： G06T1/20 ,  G06F16/9027 ,  G06F9/3877 ,  G06F9/3891 ,  G06F9/5077 ,  G06T15/005 ,  G06T15/06

摘要： An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20210287419A1

公开(公告)日：2021-09-16

申请号：US17159399

申请日：2021-01-27

申请人： Intel Corporation

发明人： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC分类号： G06T15/00 ,  G06T1/60 ,  G06T15/06

摘要： Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.