公开(公告)号：US20250006668A1

公开(公告)日：2025-01-02

申请号：US18342112

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/66 ,  H01L23/528

Abstract: Waveguide structures are built into integrated circuit devices using standard processing steps for semiconductor device fabrication. A waveguide may include a base, a top, and two side walls. At least one of the walls (e.g., the base or the top) may be formed in a metal layer. The base or top may be patterned to provide a transition to a planar transmission line, such as a coplanar waveguide. The side walls may be formed using vias.

公开(公告)号：US20240387353A1

公开(公告)日：2024-11-21

申请号：US18320763

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Michael Langenbuch ,  Carla Moran Guizan ,  Mamatha Yakkegondi Virupakshappa ,  Roshini Sachithanandan ,  Philipp Riess ,  Jonathan Jensen ,  Peter Baumgartner ,  Georg Seidemann

IPC: H01L23/522 ,  H01L23/66

Abstract: Methods and apparatus are disclosed for implementing capacitors in semiconductor devices. An example semiconductor die includes a first dielectric material disposed between a first metal interconnect and a second metal interconnect; and a capacitor positioned within a via extending through the first dielectric material between the first and second metal interconnects, the capacitor including a second dielectric material disposed in the via between the first and second metal interconnects.

公开(公告)号：US20250006630A1

公开(公告)日：2025-01-02

申请号：US18342130

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Thomas Wagner ,  Georg Seidemann ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.

公开(公告)号：US20230197615A1

公开(公告)日：2023-06-22

申请号：US17557134

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Peter Baumgartner ,  Bernd Waidhas ,  Wolfgang Molzer ,  Klaus Herold ,  Joachim Singer ,  Michael Langenbuch ,  Thomas Wagner

IPC: H01L23/528 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/645 ,  H01L23/5226

Abstract: IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.

公开(公告)号：US20240429221A1

公开(公告)日：2024-12-26

申请号：US18339685

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Thomas Wagner ,  Georg Seidemann ,  Nicolas Richaud ,  Manisha Dutta ,  Georgios Dogiamis ,  Harshit Dhakad ,  Michael Langenbuch

IPC: H01L25/18 ,  H01L23/31 ,  H01L25/00 ,  H01L27/01 ,  H01Q1/22 ,  H01Q9/04

Abstract: Glass layers and capacitors for use with integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a semiconductor die, a glass layer, and a capacitor electrically coupled to the semiconductor die, at least one side of the capacitor enclosed by the glass layer, the capacitor positioned closer to the glass layer than the semiconductor die is to the glass layer.

公开(公告)号：US20230197599A1

公开(公告)日：2023-06-22

申请号：US17554112

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Harald Gossner ,  Wolfgang Molzer ,  Georg Seidemann ,  Michael Langenbuch ,  Martin Ostermayr ,  Joachim Singer ,  Thomas Wagner ,  Klaus Herold

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.

公开(公告)号：US20230197598A1

公开(公告)日：2023-06-22

申请号：US17554004

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Georgios Panagopoulos ,  Richard Geiger ,  Peter Baumgartner ,  Harald Gossner ,  Uwe Hodel ,  Michael Langenbuch ,  Johannes Xaver Rauh ,  Alexander Bechtold ,  Richard Hudeczek ,  Carla Moran Guizan

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including inductors or transformers formed based on BPRs are disclosed. An example IC device includes semiconductor structures of one or more transistors, an electrically conductive layer, a support structure comprising a semiconductor material, and an inductor. The inductor includes an electrical conductor constituted by a power rail buried in the support structure. The inductor also includes a magnetic core coupled to the electrical conductor. The magnetic core includes magnetic rails buried in the support structure, magnetic TSVs buried in the support structure, and a magnetic plate at the backside of the support structure. The magnetic core includes a magnetic material, such as Fe, NiFe, CoZrTa, etc. In some embodiments, the IC device includes another power rail that is buried in the support structure and constitutes another electrical conductor coupled to the magnetic core. The two power rails and magnetic core can constitute a transformer.