公开(公告)号：US20230197615A1

公开(公告)日：2023-06-22

申请号：US17557134

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Peter Baumgartner ,  Bernd Waidhas ,  Wolfgang Molzer ,  Klaus Herold ,  Joachim Singer ,  Michael Langenbuch ,  Thomas Wagner

IPC: H01L23/528 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/645 ,  H01L23/5226

Abstract: IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.

公开(公告)号：US12057411B2

公开(公告)日：2024-08-06

申请号：US16721095

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Stephan Stoeckl ,  Wolfgang Molzer ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L23/58 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L28/40 ,  H01L24/13 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/13024

Abstract: Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.

公开(公告)号：US20230307313A1

公开(公告)日：2023-09-28

申请号：US17703400

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Wolfgang Molzer ,  Stefan Reif ,  Georg Seidemann ,  Stephan Stoeckl ,  Pouya Talebbeydokhti

IPC: H01L23/373 ,  H01L23/367

CPC classification number: H01L23/3732 ,  H01L23/367

Abstract: A semiconductor package comprises a package substrate comprised of at least a first layer of dielectric material including a portion of diamond dust material. The diamond dust material is comprised of diamond dust particles. The semiconductor package includes at least one electrical connection coupled through layers of the package substrate.

公开(公告)号：US20230300975A1

公开(公告)日：2023-09-21

申请号：US17699211

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Jan Proschwitz ,  Sonja Koller ,  Thomas Wagner ,  Vishnu Prasad ,  Wolfgang Molzer

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L25/18 ,  H05K3/30 ,  H05K1/18

CPC classification number: H05K1/0284 ,  H01L21/4803 ,  H01L23/13 ,  H01L25/0652 ,  H01L25/18 ,  H05K3/305 ,  H05K1/181 ,  H01L25/0657 ,  H01L24/16

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.

公开(公告)号：US20160148920A1

公开(公告)日：2016-05-26

申请号：US15009731

申请日：2016-01-28

Applicant: Intel Corporation

Inventor： Reinhard Mahnkopf ,  Wolfgang Molzer ,  Bernd Memmler ,  Edmund Goetz ,  Hans-Joachim Barth ,  Sven Albers ,  Thorsten Meyer

IPC: H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

公开(公告)号：US20230317544A1

公开(公告)日：2023-10-05

申请号：US17700211

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Jan Proschwitz ,  Sonja Koller ,  Thomas Wagner ,  Vishnu Prasad ,  Wolfgang Molzer

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/367

CPC classification number: H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/18 ,  H01L24/73 ,  H01L2224/73204

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a first surface including a cavity and an opposing second surface; a die above the cavity and electrically coupled to the second surface of the substrate; a circuit board attached to the substrate; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die. In some embodiments, a microelectronic assembly may include a circuit board having a surface including a cavity; a substrate having a first surface attached to the circuit board and a die electrically coupled to an opposing second surface; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die.

公开(公告)号：US20230298953A1

公开(公告)日：2023-09-21

申请号：US17699139

申请日：2022-03-20

Applicant: Intel Corporation

Inventor： Pouya Talebbeydokhti ,  Mohan Prashanth Javare Gowda ,  Sonja Koller ,  Stephan Stoeckl ,  Thomas Wagner ,  Wolfgang Molzer

IPC: H01L23/053 ,  H01L23/00 ,  H01L25/10 ,  H01L23/06 ,  H01L23/10

CPC classification number: H01L23/053 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L23/06 ,  H01L23/10 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16237 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2924/1611 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/16315 ,  H01L2924/1632

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

公开(公告)号：US20230197599A1

公开(公告)日：2023-06-22

申请号：US17554112

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Harald Gossner ,  Wolfgang Molzer ,  Georg Seidemann ,  Michael Langenbuch ,  Martin Ostermayr ,  Joachim Singer ,  Thomas Wagner ,  Klaus Herold

IPC: H01L23/522 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0924

Abstract: IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.

公开(公告)号：US09373588B2

公开(公告)日：2016-06-21

申请号：US14034854

申请日：2013-09-24

Applicant: Intel Corporation

Inventor： Reinhard Mahnkopf ,  Wolfgang Molzer ,  Bernd Memmler ,  Edmund Goetz ,  Hans-Joachim Barth ,  Sven Albers ,  Thorsten Meyer

IPC: H01L29/40 ,  H01L23/538 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

Abstract translation: 本说明书的实施例包括嵌入在微电子衬底中的堆叠微电子骰子及其制造方法。 在一个实施例中，至少一个第一微电子管芯连接到第二微电子管芯，其中在第二微电子管芯和至少一个第一微电子管芯之间提供底部填充材料。 然后通过将第一微电子管芯和第二微电子管芯层压在衬底材料中来形成微电子衬底。

公开(公告)号：US20230268291A1

公开(公告)日：2023-08-24

申请号：US17679189

申请日：2022-02-24

Applicant: Intel Corporation

Inventor： Mohan Prashanth Javare Gowda ,  Stephan Stoeckl ,  Sonja Koller ,  Wolfgang Molzer ,  Thomas Wagner ,  Pouya Talebbeydokhti

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/552

Abstract: Embodiments of a microelectronic assembly include a package substrate comprising: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material, the second plurality of mutually parallel channels being orthogonal to the first plurality of mutually parallel channels. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer and the third layer comprises a second material different from the first material.