公开(公告)号：US20240347465A1

公开(公告)日：2024-10-17

申请号：US18753766

申请日：2024-06-25

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Nicholas J. KYBERT ,  Mohit K. HARAN ,  Hiten KOTHARI

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/51

CPC classification number: H01L23/535 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/518 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0276 ,  H01L21/31144 ,  H01L29/45

Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.

公开(公告)号：US20250112037A1

公开(公告)日：2025-04-03

申请号：US18374603

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Mark KOEPER ,  Andrew MOORE ,  Sreenivas KOSARAJU ,  Nicholas J. KYBERT ,  Mengcheng LU ,  Atul MADHAVAN ,  Sudipto NASKAR ,  Wei Z. QIU ,  Tiffany R. ZINK

IPC: H01L21/02 ,  H01L23/48 ,  H01L29/10 ,  H01L29/423

Abstract: Selective dielectric growth directing contact to gate or contact to trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures and have an uppermost surface above an uppermost surface of gate electrodes of the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric-on-metal (DOM) layer is on and is confined to the uppermost surface of the conductive trench contact structures. A gate contact via is on a gate electrode of one of the plurality of gate structures.

公开(公告)号：US20240006322A1

公开(公告)日：2024-01-04

申请号：US18370198

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Nicholas J. KYBERT ,  Mohit K. HARAN ,  Hiten KOTHARI

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51

CPC classification number: H01L23/535 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/518 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0276

Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.

公开(公告)号：US20220310516A1

公开(公告)日：2022-09-29

申请号：US17841479

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Nicholas J. KYBERT ,  Mohit K. HARAN ,  Hiten KOTHARI

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51

Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.